公开(公告)号：US5976929A

公开(公告)日：1999-11-02

申请号：US962878

申请日：1997-11-03

申请人： Kazuhiko Kajigaya ,  Masayuki Nakamura ,  Toshikazu Tachibana ,  Goro Kitsukawa

发明人： Kazuhiko Kajigaya ,  Masayuki Nakamura ,  Toshikazu Tachibana ,  Goro Kitsukawa

IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/105 ,  H01L27/10805

摘要： A semiconductor integrated circuit device having a DRAM consisting of memory cells, comprises; a first conductive film deposited over the main surface of a semiconductor substrate and used to form a gate electrode of a memory cell selection MISFET; a second conductive film deposited over the first conductive film and used to form bit lines to transfer data of a memory cell to a sense amplifier; a third conductive film deposited over the second conductive film and used to form a storage node of a capacitor; a fourth conductive film deposited over the third conductive film and used to form a plate electrode of the capacitor; and a fifth conductive film deposited over the fourth conductive film and used to form an interconnect, wherein a transistor in a direct peripheral circuit arranged close to a memory array is electrically connected, through a pad layer formed of the third conductive film, to the interconnection of the fifth conductive film deposited over the fourth conductive film, thereby allowing the aspect ratio of the contact hole formed over the pad layer to be reduced.

摘要翻译： 一种具有由存储单元组成的DRAM的半导体集成电路器件，包括： 沉积在半导体衬底的主表面上并用于形成存储器单元选择MISFET的栅电极的第一导电膜; 沉积在第一导电膜上并用于形成位线以将存储器单元的数据传送到读出放大器的第二导电膜; 沉积在所述第二导电膜上并用于形成电容器的存储节点的第三导电膜; 沉积在所述第三导电膜上并用于形成所述电容器的平板电极的第四导电膜; 以及沉积在第四导电膜上并用于形成互连的第五导电膜，其中布置在存储器阵列附近的直接外围电路中的晶体管通过由第三导电膜形成的焊盘层电连接到互连 所述第五导电膜沉积在所述第四导电膜上，从而允许形成在所述焊盘层上的所述接触孔的纵横比减小。

公开(公告)号：US5604365A

公开(公告)日：1997-02-18

申请号：US297039

申请日：1994-08-29

申请人： Kazuhiko Kajigaya ,  Masayuki Nakamura ,  Toshikazu Tachibana

发明人： Kazuhiko Kajigaya ,  Masayuki Nakamura ,  Toshikazu Tachibana

IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/105 ,  H01L27/10805

摘要： A semiconductor integrated circuit device having a DRAM consisting of memory cells, comprises; a first conductive film deposited over the main surface of a semiconductor substrate and used to form a gate electrode of a memory cell selection MISFET; a second conductive film deposited over the first conductive film and used to form bit lines to transfer data of a memory cell to a sense amplifier; a third conductive film deposited over the second conductive film and used to form a storage node of a capacitor; a fourth conductive film deposited over the third conductive film and used to form a plate electrode of the capacitor; and a fifth conductive film deposited over the fourth conductive film and used to form an interconnect, wherein a transistor in a direct peripheral circuit arranged close to a memory array is electrically connected, through a pad layer formed of the third conductive film, to the interconnection of the fifth conductive film deposited over the fourth conductive film, thereby allowing the aspect ratio of the contact hole formed over the pad layer to be reduced.

摘要翻译： 一种具有由存储单元组成的DRAM的半导体集成电路器件，包括： 沉积在半导体衬底的主表面上并用于形成存储器单元选择MISFET的栅电极的第一导电膜; 沉积在第一导电膜上并用于形成位线以将存储器单元的数据传送到读出放大器的第二导电膜; 沉积在所述第二导电膜上并用于形成电容器的存储节点的第三导电膜; 沉积在所述第三导电膜上并用于形成所述电容器的平板电极的第四导电膜; 以及沉积在第四导电膜上并用于形成互连的第五导电膜，其中布置在存储器阵列附近的直接外围电路中的晶体管通过由第三导电膜形成的焊盘层电连接到互连 所述第五导电膜沉积在所述第四导电膜上，从而允许形成在所述焊盘层上的所述接触孔的纵横比减小。

公开(公告)号：US06195305B1

公开(公告)日：2001-02-27

申请号：US09288512

申请日：1999-04-08

申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

IPC分类号： G11C700

CPC分类号： G11C5/147

摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

公开(公告)号：US06584031B2

公开(公告)日：2003-06-24

申请号：US10107139

申请日：2002-03-28

申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

IPC分类号： G11C700

CPC分类号： G11C5/147

摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

公开(公告)号：US06385118B2

公开(公告)日：2002-05-07

申请号：US09907929

申请日：2001-07-19

申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

IPC分类号： G11C700

CPC分类号： G11C5/147

摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

公开(公告)号：US06288967B1

公开(公告)日：2001-09-11

申请号：US09742078

申请日：2000-12-22

申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

IPC分类号： G11C700

摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

公开(公告)号：US06680875B2

公开(公告)日：2004-01-20

申请号：US10259579

申请日：2002-09-30

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C800

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.

摘要翻译： 一种半导体器件，包括多个存储体和对应于存储体的多个电源电路。 每个存储体被激活命令独立地激活。 给定外部提供的电压，每个电源电路输出预定的内部电源电压。 每个电源电路的输出连接到相应的存储体。 响应于用于激活存储体之一的命令，相应的电源电路被激活，而剩余的电源电路被去激活。

公开(公告)号：US5905685A

公开(公告)日：1999-05-18

申请号：US951734

申请日：1997-10-15

申请人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

发明人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C11/408 ,  G11C11/4087

摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.

摘要翻译： 在具有存储单元阵列的动态RAM中，其中动态存储单元布置在字线和一对位线中的一个位线之间的交叉点处，对应于电源电压的选择电平信号和对应于 低于电路接地电位的负电位被提供给字线。 通过由电路接地电位进行工作的读出放大器对一对位线读取的存储单元的信号和通过将电源电压降低等于地址选择MOSFET的阈值电压的量而形成的内部电压被放大。 动态RAM具有接收电源电压和电路接地电位的振荡器，以及接收由振荡器产生的振荡脉冲以产生负电位的电路。

公开(公告)号：US07688670B2

公开(公告)日：2010-03-30

申请号：US12165681

申请日：2008-07-01

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

摘要翻译： 提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。 在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。 当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。 然而，第二电源电路在掉电模式期间连续运行。 在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

公开(公告)号：US07411856B2

公开(公告)日：2008-08-12

申请号：US11727430

申请日：2007-03-27

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

摘要翻译： 提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。 在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。 当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。 然而，第二电源电路在掉电模式期间连续运行。 在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。