公开(公告)号：US20100311238A1

公开(公告)日：2010-12-09

申请号：US12859018

申请日：2010-08-18

申请人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

发明人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

IPC分类号： H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L27/124 ,  H01L27/1292 ,  H01L27/1296 ,  H01L29/458

摘要： A method of forming a copper wiring layer, which includes forming a pattern of copper seed layer on a substrate, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating. At least one component of semiconductor device selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected with at least one of these electrodes is formed by a method comprising forming a pattern of copper seed layer, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating.

摘要翻译： 一种形成铜布线层的方法，其包括在基板上形成铜籽晶层的图案，并通过无电镀在铜籽晶层的图案上形成铜布线图案。 通过包括形成铜籽晶层的图案的方法，形成从由栅电极，源电极，漏电极和与这些电极中的至少一个连接的布线的组中选择的至少一个半导体器件的组件， 并通过无电镀法在铜籽晶层的图案上形成铜布线图案。

公开(公告)号：US20070072417A1

公开(公告)日：2007-03-29

申请号：US11531873

申请日：2006-09-14

申请人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

发明人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A method for forming a wiring structure includes forming a metal layer on a substrate, and annealing the metal layer by irradiating the metal layer with light emitted from at least one flash tube, thereby growing crystalline grains of the metal layer.

摘要翻译： 一种形成布线结构的方法包括：在基板上形成金属层，并且通过用从至少一个闪光管发射的光照射金属层来对金属层进行退火，从而生长金属层的晶粒。

公开(公告)号：US07790612B2

公开(公告)日：2010-09-07

申请号：US11531873

申请日：2006-09-14

申请人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

发明人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

IPC分类号： H01L21/4763 ,  H01L21/00

CPC分类号： H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A method for forming a wiring structure includes forming a metal layer on a substrate, and annealing the metal layer by irradiating the metal layer with light emitted from at least one flash tube, thereby growing crystalline grains of the metal layer.

摘要翻译： 一种形成布线结构的方法包括：在基板上形成金属层，并且通过用从至少一个闪光管发射的光照射金属层来对金属层进行退火，从而生长金属层的晶粒。

公开(公告)号：US20100301342A1

公开(公告)日：2010-12-02

申请号：US12851290

申请日：2010-08-05

申请人： Hiroki NAKAMURA ,  Masaki Kado ,  Shigeru Aomori

发明人： Hiroki NAKAMURA ,  Masaki Kado ,  Shigeru Aomori

IPC分类号： H01L23/52 ,  H01L27/12

CPC分类号： H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A method for forming a wiring structure includes forming a metal layer on a substrate, and annealing the metal layer by irradiating the metal layer with light emitted from at least one flash tube, thereby growing crystalline grains of the metal layer.

摘要翻译： 一种形成布线结构的方法包括：在基板上形成金属层，并且通过用从至少一个闪光管发射的光照射金属层来对金属层进行退火，从而生长金属层的晶粒。

公开(公告)号：US20060178007A1

公开(公告)日：2006-08-10

申请号：US11344014

申请日：2006-02-01

申请人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

发明人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

IPC分类号： H01L21/44

CPC分类号： H01L21/76885 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L27/124 ,  H01L27/1292 ,  H01L27/1296 ,  H01L29/458

摘要： A method of forming a copper wiring layer, which includes forming a pattern of copper seed layer on a substrate, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating. At least one component of semiconductor device selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected with at least one of these electrodes is formed by a method comprising forming a pattern of copper seed layer, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating.

摘要翻译： 一种形成铜布线层的方法，其包括在基板上形成铜籽晶层的图案，并通过无电镀在铜籽晶层的图案上形成铜布线图案。 通过包括形成铜籽晶层的图案的方法，形成从由栅电极，源电极，漏电极和与这些电极中的至少一个连接的布线的组中选择的至少一个半导体器件的组件， 并通过无电镀法在铜籽晶层的图案上形成铜布线图案。

公开(公告)号：US07138715B2

公开(公告)日：2006-11-21

申请号：US10974722

申请日：2004-10-28

申请人： Masaki Kado ,  Shigeru Aomori ,  Yoshitaka Yamamoto

发明人： Masaki Kado ,  Shigeru Aomori ,  Yoshitaka Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L29/4908 ,  H01L21/4846 ,  H01L23/498 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect forming method according to the present invention includes a step of forming a barrier film for metal diffusion on an insulator film, a step of selectively forming a metal seed layer on the barrier film for metal diffusion using an electroless plating process, a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process, and a step of etching the barrier film for metal diffusion using the metal conductive layer as a mask.

摘要翻译： 根据本发明的互连形成方法包括在绝缘膜上形成用于金属扩散的阻挡膜的步骤，使用化学镀处理在用于金属扩散的阻挡膜上选择性地形成金属籽晶层的步骤， 使用电镀工艺在所述金属种子层上选择性地形成金属导电层，以及使用所述金属导电层作为掩模来蚀刻用于金属扩散的阻挡膜的步骤。

公开(公告)号：US06890849B2

公开(公告)日：2005-05-10

申请号：US10660702

申请日：2003-09-12

申请人： Masaki Kado ,  Shigeru Aomori ,  Yoshitaka Yamamoto

发明人： Masaki Kado ,  Shigeru Aomori ,  Yoshitaka Yamamoto

IPC分类号： G02F1/136 ,  H01L21/336 ,  H01L21/48 ,  H01L23/498 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/40

CPC分类号： H01L29/4908 ,  H01L21/4846 ,  H01L23/498 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect forming method according to the present invention includes a step of forming a barrier film for metal diffusion on an insulator film, a step of selectively forming a metal seed layer on the barrier film for metal diffusion using an electroless plating process, a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process, and a step of etching the barrier film for metal diffusion using the metal conductive layer as a mask.

公开(公告)号：US20050082538A1

公开(公告)日：2005-04-21

申请号：US10974722

申请日：2004-10-28

申请人： Masaki Kado ,  Shigeru Aomori ,  Yoshitaka Yamamoto

发明人： Masaki Kado ,  Shigeru Aomori ,  Yoshitaka Yamamoto

IPC分类号： G02F1/136 ,  H01L21/336 ,  H01L21/48 ,  H01L23/498 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/4908 ,  H01L21/4846 ,  H01L23/498 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect forming method according to the present invention includes a step of forming a barrier film for metal diffusion on an insulator film, a step of selectively forming a metal seed layer on the barrier film for metal diffusion using an electroless plating process, a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process, and a step of etching the barrier film for metal diffusion using the metal conductive layer as a mask.

摘要翻译： 根据本发明的互连形成方法包括在绝缘膜上形成用于金属扩散的阻挡膜的步骤，使用化学镀处理在用于金属扩散的阻挡膜上选择性地形成金属籽晶层的步骤， 使用电镀工艺在所述金属种子层上选择性地形成金属导电层，以及使用所述金属导电层作为掩模来蚀刻用于金属扩散的阻挡膜的步骤。

公开(公告)号：US08085355B2

公开(公告)日：2011-12-27

申请号：US12547340

申请日：2009-08-25

申请人： Hajime Watakabe ,  Masato Hiramatsu ,  Toshiya Kiyota ,  Mikio Murata ,  Masaki Kado ,  Arichika Ishida ,  Yoshiaki Nakazaki

发明人： Hajime Watakabe ,  Masato Hiramatsu ,  Toshiya Kiyota ,  Mikio Murata ,  Masaki Kado ,  Arichika Ishida ,  Yoshiaki Nakazaki

IPC分类号： G02F1/136

CPC分类号： H01L27/124 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2202/104 ,  H01L29/42384

摘要： A structure of a plurality of thin film transistors wherein a peripheral circuit on a glass substrate of a liquid crystal display panel; and each of polycrystalline silicon thin film 13 of the thin film transistor is formed on the glass substrate; and each of gate electrode 15 is formed on a gate insulation layer, and each of the gate electrode 15 is overhead corresponding to the polycrystalline silicon thin film 13 for a channel; wherein the gate electrode 15 is comprised a pair of projection part 15A and a gate-channel 15B; and wherein the pair of projection part 15A is formed the both sides of the gate-channel 15B in which the side is for along the channel-direction, and wherein the pair of projection part 15A is enlarged for across the channel-direction.

摘要翻译： 多个薄膜晶体管的结构，其中液晶显示面板的玻璃基板上的外围电路; 并且在玻璃基板上形成薄膜晶体管的多晶硅薄膜13; 并且每个栅电极15形成在栅极绝缘层上，并且每个栅电极15对应于用于沟道的多晶硅薄膜13的顶部; 其中栅电极15包括一对突出部分15A和栅极通道15B; 并且其中所述一对突出部分15A形成在所述侧壁用于沿着所述通道方向的所述栅极通道15B的两侧，并且其中所述一对突出部分15A在所述通道方向上被扩大。

公开(公告)号：US20100110322A1

公开(公告)日：2010-05-06

申请号：US12547340

申请日：2009-08-25

申请人： Hajime WATAKABE ,  Masato Hiramatsu ,  Toshiya Kiyota ,  Mikio Murata ,  Masaki Kado ,  Arichika Ishida ,  Yoshiaki Nakazaki

发明人： Hajime WATAKABE ,  Masato Hiramatsu ,  Toshiya Kiyota ,  Mikio Murata ,  Masaki Kado ,  Arichika Ishida ,  Yoshiaki Nakazaki

IPC分类号： G02F1/1368 ,  H01L27/085 ,  H01L27/15

CPC分类号： H01L27/124 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2202/104 ,  H01L29/42384

摘要： A structure of a plurality of thin film transistors wherein a peripheral circuit on a glass substrate of a liquid crystal display panel; and each of polycrystalline silicon thin film 13 of the thin film transistor is formed on the glass substrate; and each of gate electrode 15 is formed on a gate insulation layer, and each of the gate electrode 15 is overhead corresponding to the polycrystalline silicon thin film 13 for a channel; wherein the gate electrode 15 is comprised a pair of projection part 15A and a gate-channel 15B; and wherein the pair of projection part 15A is formed the both sides of the gate-channel 15B in which the side is for along the channel-direction, and wherein the pair of projection part 15A is enlarged for across the channel-direction.

摘要翻译： 多个薄膜晶体管的结构，其中液晶显示面板的玻璃基板上的外围电路; 并且在玻璃基板上形成薄膜晶体管的多晶硅薄膜13; 并且每个栅电极15形成在栅极绝缘层上，并且每个栅电极15对应于用于沟道的多晶硅薄膜13的顶部; 其中栅电极15包括一对突出部分15A和栅极通道15B; 并且其中所述一对突出部分15A形成在所述侧壁用于沿着所述通道方向的所述栅极通道15B的两侧，并且其中所述一对突出部分15A在所述通道方向上被扩大。