公开(公告)号：US07462911B2

公开(公告)日：2008-12-09

申请号：US11561652

申请日：2006-11-20

申请人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

发明人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0696 ,  H01L29/7397

摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.

摘要翻译： 公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。 它包括通过沟槽分成不同p型基极区的p型基极层。 仅在一些p型基区中形成N型源极区。 在沟槽IGBT的有源区域中有一个栅极流道。 形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。 与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关，由式25 <= {N1 /（N1 + N2）}×100 <= 75。

公开(公告)号：US06737705B2

公开(公告)日：2004-05-18

申请号：US09843251

申请日：2001-04-26

申请人： Seiji Momota ,  Yuichi Onozawa ,  Masahito Otsuki ,  Hiroki Wakimoto

发明人： Seiji Momota ,  Yuichi Onozawa ,  Masahito Otsuki ,  Hiroki Wakimoto

IPC分类号： H01L29745

CPC分类号： H01L29/7397 ,  H01L29/1095 ,  H01L29/407

摘要： A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate. The ratio of the width of the first regions to the width of the second regions of p-type base layer is from 1:2 to 1:7. The device facilitates in reducing the total losses by reducing the switching loss while suppressing the on-voltage thereof as low as the on-voltage of the IEGT.

摘要翻译： 沟槽型IGBT包括硅衬底，硅衬底上的轻掺杂n型漂移层和n型漂移层上的p型基极层。 p型基极层比n型漂移层掺杂更多，由第一区域和第二区域形成。 在p型基底层的第一区域的表面部分中选择性地形成N +型源极区域。 沟槽从n +型源区的表面通过p型基底层向下到达n型漂移层。 栅极氧化膜覆盖每个沟槽的内表面。 栅极设置在沟槽中，其中栅电极经由相应的栅氧化膜面对p型基极层。 发射极电极与p型基极层和n +型源极区域的第一区域直接接触。 集电极设置在硅衬底的背面上。 第一区域的宽度与p型基底层的第二区域的宽度的比例为1:2至1:7。 该器件通过降低开关损耗同时将其导通电压抑制得低至IEGT的导通电压，从而有助于降低总损耗。

公开(公告)号：US07151297B2

公开(公告)日：2006-12-19

申请号：US10993146

申请日：2004-11-19

申请人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

发明人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0696 ,  H01L29/7397

摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.

摘要翻译： 公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。 它包括通过沟槽分成不同p型基极区的p型基极层。 仅在一些p型基区中形成N型源极区。 在沟槽IGBT的有源区域中有一个栅极流道。 形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。 与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关联，通过表达式25 <= {N1 /（N1 + N2x100 <= 75。

公开(公告)号：US20050151187A1

公开(公告)日：2005-07-14

申请号：US10993146

申请日：2004-11-19

申请人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

发明人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/76

CPC分类号： H01L29/0696 ,  H01L29/7397

摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.

摘要翻译： 公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。 它包括通过沟槽分成不同p型基极区的p型基极层。 仅在一些p型基区中形成N型源极区。 在沟槽IGBT的有源区域中存在栅极流道。 形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。 与发射电极电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关联，表达式25 <= {N1 /（N1 + N2x100 <= 75。

公开(公告)号：US06559023B2

公开(公告)日：2003-05-06

申请号：US10073528

申请日：2002-02-11

申请人： Masahito Otsuki ,  Seiji Momota ,  Mitsuaki Kirisawa ,  Takashi Yoshimura

发明人： Masahito Otsuki ,  Seiji Momota ,  Mitsuaki Kirisawa ,  Takashi Yoshimura

IPC分类号： H01L218238

CPC分类号： H01L29/66333

摘要： A method for manufacturing a semiconductor device constituting an JGHT is provided that allows to manufacture the device using an inexpensive wafer and with high yields, and achieves low losses. Specifically, after an emitter electrode is formed, a reverse principal surface is polished to a specified thickness. The center line average height Ra of the polished surface is controlled to be not more than 1 &mgr;m, and the filtered center line waviness Wca is kept within 10 &mgr;m. The polished surface is selectively cleaned with an aqueous chemical solution to remove particles. To the cleaned surface, phosphorus ions arc implanted for forming a field-stop layer and boron ions are implanted for forming a collector layer. The wafer is then put into a diffusion furnace and annealed at a temperature from 300° C. to 550° C. to form a field-stop layer and a collector layer. Finally, a collector electrode is formed.

摘要翻译： 提供了一种制造构成JGHT的半导体器件的方法，其允许使用廉价的晶片以高产率制造器件，并且实现低损耗。 具体地说，在形成发射电极之后，将反向主表面抛光至规定的厚度。 研磨面的中心线平均高度Ra被控制在1um以下，经滤波的中心线波纹Wca保持在10um以内。 用水性化学溶液选择性地清洁抛光表面以除去颗粒。 在清洁表面上，注入磷离子以形成场阻止层，并注入硼离子以形成集电极层。 然后将晶片放入扩散炉中并在300℃至550℃的温度下退火以形成场停止层和集电极层。 最后，形成集电极。

公开(公告)号：US5559355A

公开(公告)日：1996-09-24

申请号：US492854

申请日：1995-06-20

申请人： Tomoyuki Yamazaki ,  Shigeyuki Obinata ,  Masahito Otsuki ,  Seiji Momota ,  Tatsuhiko Fujihira

发明人： Tomoyuki Yamazaki ,  Shigeyuki Obinata ,  Masahito Otsuki ,  Seiji Momota ,  Tatsuhiko Fujihira

IPC分类号： H01L27/02 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L27/0248 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/7802

摘要： Mutual interference is reduced between a main cell portion and a sensing cell portion for detecting the current flowing through the main cell portion of a vertical MOS semiconductor device, and accuracy and reliability of overcurrent detection are improved. In the device, well regions of (p) type are formed between the main and sensing cell portions for capturing the minority carriers. Breakdown of the gate oxide film caused by an open emitter electrode of the sensing cell portion is prevented by forming the (p) type well regions with ring shapes, by spacing the (p) type well regions by 5 to 20 .mu.m, and by adjusting the isolation withstand voltage between the main and sensing cell portions below the withstand voltage of the gate oxide film. A voltage spike is minimized by narrowing the overlap of the detecting and gate electrodes for reduced capacitance between these electrodes.

摘要翻译： 在主单元部分和用于检测流过垂直MOS半导体器件的主单元部分的电流的感测单元部分之间相互干扰减小，并且提高了过电流检测的精度和可靠性。 在该器件中，（p）型的阱区形成在用于俘获少数载流子的主单元部分和感测单元部分之间。 通过将（p）型阱区间隔5〜20μm，通过形成具有环形的（p）型阱区来防止由感测单元部分的开放发射极引起的栅极氧化膜的击穿，并且通过 将主感测单元部分和感测单元部分之间的隔离耐压调节到栅极氧化膜的耐受电压以下。 通过缩小检测电极和栅电极的重叠以减小这些电极之间的电容，使电压尖峰最小化。

公开(公告)号：US06621120B2

公开(公告)日：2003-09-16

申请号：US10073683

申请日：2002-02-11

申请人： Masahito Otsuki ,  Seiji Momota ,  Mitsuaki Kirisawa ,  Takashi Yoshimura

发明人： Masahito Otsuki ,  Seiji Momota ,  Mitsuaki Kirisawa ,  Takashi Yoshimura

IPC分类号： H01L2974

CPC分类号： H01L29/66333 ,  H01L29/7395

摘要： A semiconductor device constituting an IGBT exhibits low losses yet can be manufactured using an inexpensive wafer and with high yields, and exhibits low losses. The IGBT is produced by using a wafer, for example an FZ wafer, that is cut form an ingot and has its surface polished and cleaned, wherein an n-type impurity diffusion layer having an enough dose to stop the electric field in turn-off is provided between a collector layer and a base layer as a field-stop layer for stopping an electric field in turn-off. The thickness of this field-stop layer defined by Xfs−Xj is controlled in the range from 0.5 &mgr;m to 3 &mgr;m, where Xfs is the position at which the impurity concentration in the field-stop layer is twice the impurity concentration of the base layer, and Xj is the position of the junction between the filed-stopping layer and the collector layer.

公开(公告)号：US08309409B2

公开(公告)日：2012-11-13

申请号：US13027761

申请日：2011-02-15

申请人： Seiji Momota

发明人： Seiji Momota

IPC分类号： H01L21/338 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0856 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.

摘要翻译： 半导体器件制造方法包括在第一导电性的第一半导体区域的表面层上形成具有高于第一半导体区域的杂质浓度的第二半导体区域的第二导电性区域; 形成穿过所述第二半导体区域的沟槽到所述第一半导体区域; 在第二半导体区域的表面以下的高度处经由绝缘膜将第一电极嵌入沟槽内; 在所述沟槽内形成层间绝缘膜，覆盖所述第一电极; 仅在第一电极的表面上留下层间绝缘膜; 去除所述第二半导体区域使得其表面定位成低于所述第一电极和所述层间绝缘膜之间的界面; 以及通过沟槽中的绝缘膜形成与第二半导体区域接触并与第一电极相邻的第二电极。

公开(公告)号：US20110207296A1

公开(公告)日：2011-08-25

申请号：US13027761

申请日：2011-02-15

申请人： Seiji Momota

发明人： Seiji Momota

IPC分类号： H01L21/36

CPC分类号： H01L29/7813 ,  H01L29/0856 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.

摘要翻译： 半导体器件制造方法包括在第一导电性的第一半导体区域的表面层上形成具有高于第一半导体区域的杂质浓度的第二半导体区域的第二导电性区域; 形成穿过所述第二半导体区域的沟槽到所述第一半导体区域; 在第二半导体区域的表面以下的高度，经由绝缘膜将第一电极嵌入沟槽内; 在所述沟槽内形成层间绝缘膜，覆盖所述第一电极; 仅在第一电极的表面上留下层间绝缘膜; 去除所述第二半导体区域使得其表面定位成低于所述第一电极和所述层间绝缘膜之间的界面; 以及通过沟槽中的绝缘膜形成与第二半导体区域接触并与第一电极相邻的第二电极。

公开(公告)号：US20110012195A1

公开(公告)日：2011-01-20

申请号：US12865330

申请日：2009-01-28

申请人： Seiji Momota ,  Hitoshi Abe ,  Takashi Shiigi ,  Takeshi Fujii ,  Koh Yoshikawa ,  Tetsutaro Imagawa ,  Masaki Koyama ,  Makoto Asai

发明人： Seiji Momota ,  Hitoshi Abe ,  Takashi Shiigi ,  Takeshi Fujii ,  Koh Yoshikawa ,  Tetsutaro Imagawa ,  Masaki Koyama ,  Makoto Asai

IPC分类号： H01L27/11

CPC分类号： H01L27/0629 ,  H01L27/0658 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7815 ,  H01L29/7827

摘要： Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

摘要翻译： 在主装置（24）的源电极（25）和电流检测装置（21）的电流检测电极（22）之间连接用于检测电流的电阻器。 栅极绝缘体（36）的介电耐受电压大于电阻器和流过电流检测装置（21）的反向偏压的最大电流的乘积。 主装置（24）的p体区域（32）的扩散长度短于电流检测装置（21）的p体（31）的扩散长度。 主装置（24）的p体区域（32）的端部的曲率半径比电流检测装置（21）的p体（31）的曲率半径小。 结果，在逆偏压下，主装置（24）的p体区域（32）的端部的电场变得比电流检测装置的p体区域（31）的电场强 21）。 因此，主装置24中的雪崩击穿比电流检测装置（21）更容易发生。