公开(公告)号：US07910985B2

公开(公告)日：2011-03-22

申请号：US12759858

申请日：2010-04-14

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L29/76

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 沟槽栅极导电层形成为等于或高于半导体衬底的主表面。 此外，沟槽栅极的导电层形成为具有基本上平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 此外，在蚀刻半导体衬底以形成等于或高于半导体衬底的主表面的沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区和源极区。 根据本发明制造的半导体器件不会产生源极偏移。

公开(公告)号：US06818949B2

公开(公告)日：2004-11-16

申请号：US10750819

申请日：2004-01-05

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L2976

CPC分类号： H01L29/7808 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. In this method, a trench wherein a trench-gate is to be formed is formed on the main surface of the semiconductor substrate with the insulating film formed thereon with a mask; and the side surface of the insulating film is caused to retreat from the upper end of the trench by isotropic etching, whereby a gate insulating film and a conductive layer to be the trench gate are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. According to the present invention, occurrence of a source offset and damage of a gate insulating film can be prevented.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 形成比半导体衬底的主表面高的沟槽栅极导电层，并且沟槽栅极导电层和栅极绝缘膜形成在沟槽的周围的沟槽中并在半导体衬底的主表面上方。 在该方法中，在其上形成有绝缘膜的半导体衬底的主表面上形成有要形成沟槽栅的沟槽; 并且通过各向同性蚀刻使绝缘膜的侧表面从沟槽的上端退回，由此在沟槽中并在半导体的主表面上形成作为沟槽栅极的栅极绝缘膜和导电层 衬底在沟槽的周边。 根据本发明，可以防止源极偏移的发生和栅极绝缘膜的损坏。

公开(公告)号：US20100193863A1

公开(公告)日：2010-08-05

申请号：US12759858

申请日：2010-04-14

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L29/78

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 沟槽栅极导电层形成为等于或高于半导体衬底的主表面。 此外，沟槽栅极的导电层形成为具有基本上平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 此外，在蚀刻半导体衬底以形成等于或高于半导体衬底的主表面的沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区和源极区。 根据本发明制造的半导体器件不会产生源极偏移。

公开(公告)号：US20060252192A1

公开(公告)日：2006-11-09

申请号：US11483547

申请日：2006-07-11

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/266 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

公开(公告)号：US20050082608A1

公开(公告)日：2005-04-21

申请号：US10986495

申请日：2004-11-12

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L31/109

CPC分类号： H01L29/7808 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. In this method, a trench wherein a trench-gate is to be formed is formed on the main surface of the semiconductor substrate with the insulating film formed thereon with a mask; and the side surface of the insulating film is caused to retreat from the upper end of the trench by isotropic etching, whereby a gate insulating film and a conductive layer to be the trench gate are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. According to the present invention, occurrence of a source offset and damage of a gate insulating film can be prevented.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 形成比半导体衬底的主表面高的沟槽栅极导电层，并且沟槽栅极导电层和栅极绝缘膜形成在沟槽的周围的沟槽中并在半导体衬底的主表面上方。 在该方法中，在其上形成有绝缘膜的半导体衬底的主表面上形成有要形成沟槽栅的沟槽; 并且通过各向同性蚀刻使绝缘膜的侧表面从沟槽的上端退回，由此在沟槽中并在半导体的主表面上形成作为沟槽栅极的栅极绝缘膜和导电层 衬底在沟槽的周边。 根据本发明，可以防止源极偏移的发生和栅极绝缘膜的损坏。

公开(公告)号：US08378413B2

公开(公告)日：2013-02-19

申请号：US13032080

申请日：2011-02-22

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L29/76

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 沟槽栅极导电层形成为等于或高于半导体衬底的主表面。 此外，沟槽栅极的导电层形成为具有基本上平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 此外，在蚀刻半导体衬底以形成等于或高于半导体衬底的主表面的沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区和源极区。 根据本发明制造的半导体器件不会产生源极偏移。

公开(公告)号：US20080233696A1

公开(公告)日：2008-09-25

申请号：US12071542

申请日：2008-02-22

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/266 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 沟槽栅极导电层形成为等于或高于半导体衬底的主表面。 此外，沟槽栅极的导电层形成为具有基本上平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 此外，在蚀刻半导体衬底以形成等于或高于半导体衬底的主表面的沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区和源极区。 根据本发明制造的半导体器件不会产生源极偏移。

公开(公告)号：US07358141B2

公开(公告)日：2008-04-15

申请号：US11483547

申请日：2006-07-11

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/266 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

公开(公告)号：US20110140198A1

公开(公告)日：2011-06-16

申请号：US13032080

申请日：2011-02-22

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L29/78

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 沟槽栅极导电层形成为等于或高于半导体衬底的主表面。 此外，沟槽栅极的导电层形成为具有基本上平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 此外，在蚀刻半导体衬底以形成等于或高于半导体衬底的主表面的沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区和源极区。 根据本发明制造的半导体器件不会产生源极偏移。

公开(公告)号：US07098506B2

公开(公告)日：2006-08-29

申请号：US11045148

申请日：2005-01-31

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.