公开(公告)号：US07074676B2

公开(公告)日：2006-07-11

申请号：US10468738

申请日：2002-02-13

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Nobutoshi Arai ,  Takayuki Ogura ,  Kouichirou Adachi ,  Seizo Kakimoto ,  Yukio Yasuda ,  Shigeaki Zaima ,  Akira Sakai

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Nobutoshi Arai ,  Takayuki Ogura ,  Kouichirou Adachi ,  Seizo Kakimoto ,  Yukio Yasuda ,  Shigeaki Zaima ,  Akira Sakai

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332 ,  Y10S438/962

摘要： A memory film operable at a low voltage and a method of manufacturing the memory film; the method, comprising the steps of forming a first insulation film (112) on a semiconductor substrate (111) forming a first electrode, forming a first conductor film (113) on the first insulation film (112), forming a second insulation film (112B) on the surface of the first conductor film (113), forming a third insulation film containing conductor particulates (114, 115) on the second insulation film (112B), and forming a second conductor film forming a second electrode on the third insulation film.

摘要翻译： 以低电压工作的记忆膜和制造该记忆膜的方法; 该方法包括以下步骤：在形成第一电极的半导体衬底（111）上形成第一绝缘膜（112），在第一绝缘膜（112）上形成第一导体膜（113），形成第二绝缘膜（ 112B），在第二绝缘膜（112B）上形成包含导体微粒（114,115）的第三绝缘膜，并在第二绝缘膜（112B）上形成第二导电膜，形成第二电极 第三绝缘膜。

公开(公告)号：US06876055B2

公开(公告)日：2005-04-05

申请号：US10399902

申请日：2001-10-19

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H01L21/76 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/72

CPC分类号： H01L21/823481 ,  H01L21/761 ,  H01L21/76202 ,  H01L21/76232 ,  H01L21/823493

摘要： A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors (223) are formed on a P-type shallow well region (212). The depth of a shallow device isolation region (214) on the P-type shallow well region (212) is less than the depth of the junction between an N-type deep well region (227) and the P-type shallow well region (212). Therefore the field effect transistors (223) share the P-type shallow well region (212). The P-type shallow well regions (212) independently of each other are easily formed since they are isolated from each other by a deep device isolation region (226) and the N-type deep well region (227).

摘要翻译： 一种半导体器件，具有在阱区的边界处所需的两层阱结构和小的边界，并且包括衬底偏置可变晶体管和DTMOS。 场效应晶体管（223）形成在P型浅阱区（212）上。 P型浅井区域（212）上的浅装置隔离区域（214）的深度小于N型深井区域（227）和P型浅井区域（ 212）。 因此，场效应晶体管223共用P型浅阱区212。 彼此独立的P型浅阱区（212）容易形成，因为它们通过深度器件隔离区域（226）和N型深阱区域（227）彼此隔离。

公开(公告)号：US07176526B2

公开(公告)日：2007-02-13

申请号：US10899183

申请日：2004-07-27

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A–A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106。 源极区域106和漏极区域106中的至少一个具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：US07084465B2

公开(公告)日：2006-08-01

申请号：US10451744

申请日：2001-12-26

申请人： Akihide Shibata ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Akihide Shibata ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L31/113

CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892

摘要： There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions are formed in one P-type semiconductor substrate. The N-type deep well regions are electrically isolated by the P-type semiconductor substrate. Over the N-type deep well regions, a P-type deep well region and a P-type shallow well region are formed to fabricate an N-type substrate variable-bias transistor. Over the N-type deep well region, an N-type shallow well region is formed to fabricate a P-type substrate variable-bias transistor. Further a P-type DTMOS and an N-type DTMOD are fabricated.

摘要翻译： 提供了包括DTMOS和基板可变偏置晶体管的半导体器件以及可以以降低的功耗进行操作的便携式电子设备。 在一个P型半导体衬底中形成N型深阱区。 N型深阱区域由P型半导体衬底电隔离。 在N型深井区域中，形成P型深井区域和P型浅井区域，以制造N型衬底可变偏压晶体管。 在N型深井区域上，形成N型浅井区，以制造P型衬底可变偏压晶体管。 此外，还制作了P型DTMOS和N型DTMOD。

公开(公告)号：US06969893B2

公开(公告)日：2005-11-29

申请号：US10416856

申请日：2001-11-13

申请人： Akihide Shibata ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Akihide Shibata ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/76229 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0921

摘要： There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.

摘要翻译： 提供了具有DTMOS和衬底偏置可变晶体管的低功耗和高可靠性的半导体器件，以及使用该半导体器件的便携式电子设备。 在半导体衬底（11）上，形成三层阱区域（12,14,16,13,15,16），并且在所述半导体衬底（11）中提供DTMOS'（29,30）和衬底偏置可变晶体管（27,28） 浅井区域（16,17）。 在形成PNP，NPN或NPNP结构的边界处提供大宽度器件隔离区（181,182,183），其中在两侧的阱区具有相同的条件下提供小宽度器件隔离区（18） 导电型。 因此，提供各种导电类型的衬底偏置可变晶体管（27,28）的各种导电类型的多个阱区域可以彼此电独立，从而允许降低功耗。 此外，可以抑制闩锁现象。

公开(公告)号：US06787410B2

公开(公告)日：2004-09-07

申请号：US10322663

申请日：2002-12-19

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H01L218238

CPC分类号： H01L21/76229 ,  H01L21/823807 ,  H01L29/783

摘要： A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, Bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.

摘要翻译： 具有动态阈值晶体管的半导体器件包括由浅沟槽隔离构成的浅元件隔离区域和设置在浅元件隔离区域两侧的深元件隔离区域构成的复合元件隔离区域。 由于浅元件隔离区域由浅沟槽隔离构成，浅元件隔离区域中的鸟喙小。 这可以防止由于鸟嘴引起的应力引起的泄漏故障。 深元件隔离区域具有近似恒定的宽度，其允许复杂元件隔离区域宽。

公开(公告)号：US07711012B2

公开(公告)日：2010-05-04

申请号：US10467808

申请日：2002-02-13

申请人： Hiroshi Iwata ,  Tomohisa Okuno ,  Akihide Shibata ,  Seizo Kakimoto

发明人： Hiroshi Iwata ,  Tomohisa Okuno ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H04J99/00

CPC分类号： H01L27/118 ,  H01L27/0207 ,  H01L27/11898

摘要： The yield of a semiconductor device is improved which has a large-scale logic circuit or which has both a logic circuit and a memory. A basic circuit block is provided with an input/output circuit. A transmission line and a branch line connect the input/output circuits so that information can be exchanged through the input/output circuits between one basic circuit block and another basic circuit block. The memory in each basic circuit block or in each input/output circuit can be programmed from the outside to designate the destination of a signal. By thus changing the program in the memory, the transmission destination of a signal can be changed to give various functions efficiently with a limited circuit scale. Moreover, if a basic circuit block fails another basic circuit block substitutes for it to improve the yield drastically.

摘要翻译： 改善了具有大规模逻辑电路或具有逻辑电路和存储器的半导体器件的产量。 基本电路块设置有输入/输出电路。 传输线和分支线连接输入/输出电路，使得可以通过一个基本电路块和另一个基本电路块之间的输入/输出电路来交换信息。 每个基本电路块或每个输入/输出电路中的存储器可以从外部编程以指定信号的目的地。 通过这样改变存储器中的程序，可以改变信号的发送目的地，以有限的电路规模有效地提供各种功能。 此外，如果基本电路块失败，另一个基本电路块代替它可以显着提高产量。

公开(公告)号：US07352024B2

公开(公告)日：2008-04-01

申请号：US10468722

申请日：2002-02-21

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11524 ,  B82Y10/00 ,  G11C16/0416 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11568

摘要： There is provided a semiconductor storage device capable of high integration. On a top surface of a semiconductor substrate, a plurality of device isolation regions (16) each extending and meandering in a lateral direction are formed so as to be arrayed with respect to a longitudinal direction, by which active regions are defined between neighboring ones of the device isolation regions (16), respectively. Dopant diffusion regions (source or drain) are formed at individual turnover portions (corresponding to contacts (14), (15)), respectively, of the meanders within the active regions. A plurality of word lines (11) extending straight in the longitudinal direction run on the channel regions within the active regions via a film having memory function, respectively. A first bit line (12) extending straight in the lateral direction runs on the dopant diffusion region (corresponding to contact (14)) provided at a crest-side turnover portion. A second bit line (15) extending straight in the lateral direction runs on the dopant diffusion region (corresponding to contact (15)) provided at a trough-side turnover portion.

摘要翻译： 提供能够高集成度的半导体存储装置。 在半导体衬底的顶表面上形成有沿纵向方向延伸和曲折的多个器件隔离区（16），以便相对于纵向方向排列有活性区域 设备隔离区域（16）。 掺杂剂扩散区域（源极或漏极）分别形成在活性区域内的蜿蜒的各自的周转部分（对应于触点（14），（15））。 在纵向方向上直线延伸的多个字线（11）分别经由具有记忆功能的胶片在有源区域内的沟道区域上延伸。 在横向方向上直线延伸的第一位线（12）在设置在峰顶侧翻转部分的掺杂剂扩散区域（对应于触点（14））上延伸。 在横向方向上直线延伸的第二位线（15）在设置在槽侧翻转部分的掺杂剂扩散区域（对应于触点（15））上延伸。

公开(公告)号：US06825528B2

公开(公告)日：2004-11-30

申请号：US10149255

申请日：2002-08-12

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

IPC分类号： H01L2976

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅电极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106.源极区域106和漏极区域106中的至少一个 具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：US06509615B2

公开(公告)日：2003-01-21

申请号：US10067791

申请日：2002-02-08

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H01L31119

CPC分类号： H01L21/76229 ,  H01L21/823807 ,  H01L29/783

摘要： A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.

摘要翻译： 具有动态阈值晶体管的半导体器件包括由浅沟槽隔离构成的浅元件隔离区域和设置在浅元件隔离区域两侧的深元件隔离区域构成的复合元件隔离区域。 由于浅元件隔离区域由浅沟槽隔离构成，浅元件隔离区域中的鸟喙小。 这可以防止由于鸟嘴引起的应力引起的泄漏故障。 深元件隔离区域具有近似恒定的宽度，其允许复杂元件隔离区域宽。