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    SEMICONDUCTOR ELEMENT AND DEVICE USING THE SAME
    1.
    发明申请
    SEMICONDUCTOR ELEMENT AND DEVICE USING THE SAME 审中-公开
    使用相同的半导体元件和器件

    公开(公告)号：US20090073158A1

    公开(公告)日：2009-03-19

    申请号：US12212303

    申请日：2008-09-17

    申请人： Kotaro Kataoka ,  Hiroshi Iwata ,  Yoshiji Ohta ,  Kenji Kimoto ,  Kenji Komiya ,  Kouichiro Adachi ,  Akihide Shibata ,  Masatomi Harada

    发明人： Kotaro Kataoka ,  Hiroshi Iwata ,  Yoshiji Ohta ,  Kenji Kimoto ,  Kenji Komiya ,  Kouichiro Adachi ,  Akihide Shibata ,  Masatomi Harada

    IPC分类号： G09G5/00 ,  H01L29/792 ,  G05F1/10

    CPC分类号： H01L29/792 ,  H01L29/66833

    摘要： A memory element having a large memory window and a high reliability is provided at low cost by performing high speed write and erase operations at a relatively low voltage and suppressing rewrite degradation. A memory element includes a semiconductor layer arranged on an insulating substrate, a first diffusion layer region and a second diffusion layer region having a conductivity type of P-type, a charge accumulating film for covering a channel region between the first diffusion layer region and the second diffusion layer region and being injected with charges from the channel region, and a gate electrode positioned on a side opposite to the channel region with the charge accumulating film in between.

    摘要翻译： 通过在相对低的电压下执行高速写入和擦除操作并且抑制重写劣化，以低成本提供具有大存储器窗口和高可靠性的存储元件。 存储元件包括布置在绝缘基板上的半导体层，具有P型导电类型的第一扩散层区域和第二扩散层区域，用于覆盖第一扩散层区域和第二扩散层区域之间的沟道区域的电荷累积膜 第二扩散层区域，并且从沟道区域注入电荷，以及位于与沟道区相反的一侧的栅电极，电荷积聚膜在其间。

    SEMICONDUCTOR DEVICE, AND INVERTER, CONVERTER AND POWER CONVERSION DEVICE EMPLOYING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE, AND INVERTER, CONVERTER AND POWER CONVERSION DEVICE EMPLOYING THE SAME 有权
    半导体器件和逆变器，转换器和功率转换器件

    公开(公告)号：US20140028375A1

    公开(公告)日：2014-01-30

    申请号：US14110687

    申请日：2012-04-05

    申请人： Kenji Komiya ,  Shuji Wakaiki ,  Kohtaroh Kataoka ,  Masaru Nomura ,  Yoshiji Ohta ,  Hiroshi Iwata

    发明人： Kenji Komiya ,  Shuji Wakaiki ,  Kohtaroh Kataoka ,  Masaru Nomura ,  Yoshiji Ohta ,  Hiroshi Iwata

    IPC分类号： H03K17/30

    CPC分类号： H03K17/302 ,  H02M1/088 ,  H02M3/158 ,  H03K17/102 ,  H03K17/122 ,  H03K17/145

    摘要： A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.

    摘要翻译： 半导体器件包括高击穿电压，高Gm第一晶体管和低击穿电压，串联连接在第一和第二节点之间的低Gm第二晶体管和低击穿电压，并联连接到第二晶体管的高Gm第三晶体管。 当第二晶体管导通时，第一晶体管导通，此外，当第三晶体管导通时，在第一和第二节点之间建立导电状态。 第二个低击穿电压晶体管导通，以接通第一个高耐压晶体管，并且可以实现只有有限变化的导通时间。

    Semiconductor device, liquid crystal display device and electronic equipment
    10.
    发明授权
    Semiconductor device, liquid crystal display device and electronic equipment 有权
    半导体装置，液晶显示装置及电子设备

    公开(公告)号：US07804705B2

    公开(公告)日：2010-09-28

    申请号：US12022785

    申请日：2008-01-30

    申请人： Hiroshi Iwata ,  Yoshiji Ohta

    发明人： Hiroshi Iwata ,  Yoshiji Ohta

    IPC分类号： G11C11/00

    CPC分类号： G09G3/3648 ,  G09G2300/0809 ,  G09G2320/0214

    摘要： The semiconductor device of the present invention has a circuit block in which m (m is an integer of not smaller than two) sets of first through m-th transistor columns where two or more transistors are connected in series, one terminal of the first through m-th transistor columns is connected to a first output node, and the other terminal of the first through m-th transistor columns is connected to a second output node. A control signal for substantially simultaneously turning on and off all the transistors of the first through m-th transistor columns is inputted to the control input terminals of the transistors of the first through m-th transistor columns.

    摘要翻译： 本发明的半导体器件具有其中两个或多个晶体管串联连接的第一至第m晶体管列的m（m为不小于2的整数）的电路块，第一至第 第m晶体管列连接到第一输出节点，第一至第m晶体管列的另一端连接到第二输出节点。 用于基本上同时导通和关断第一至第m晶体管列的所有晶体管的控制信号被输入到第一至第三晶体管列的晶体管的控制输入端。