公开(公告)号：US07157773B2

公开(公告)日：2007-01-02

申请号：US10330093

申请日：2002-12-30

申请人： Hiroshi Kato ,  Shigehiro Kuge ,  Hideyuki Noda ,  Fukashi Morishita ,  Shuichi Ueno

发明人： Hiroshi Kato ,  Shigehiro Kuge ,  Hideyuki Noda ,  Fukashi Morishita ,  Shuichi Ueno

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L21/28282 ,  H01L29/792

摘要： A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.

摘要翻译： 非易失性半导体存储器件的存储单元通过ONO膜形成在硅衬底上形成的硅层上。 存储单元具有在硅层中形成的源区和漏区，ONO膜和栅电极。 ONO膜和ONO膜包括具有捕获电荷的电荷陷阱部分的氮化物膜。

公开(公告)号：US06483357B2

公开(公告)日：2002-11-19

申请号：US09811578

申请日：2001-03-20

申请人： Hiroshi Kato ,  Fukashi Morishita

发明人： Hiroshi Kato ,  Fukashi Morishita

IPC分类号： H03L700

CPC分类号： G05F1/465

摘要： A sense signal IVOFF is generated by a power supply level sense circuit with an external power supply potential Ext.Vcc1 as the operating power supply potential to sense the level of an external power supply potential Ext.Vcc2. By suppressing generation of an internal power supply potential or fixing the internal node by the sense signal IVOFF, the through current at the time of power on can be reduced.

摘要翻译： 感测信号IVOFF由电源电平检测电路产生，外部电源电位Ext.Vcc1作为工作电源电位，用于感测外部电源电位Ext.Vcc2的电平。 通过抑制内部电源电位的产生或通过感测信号IVOFF固定内部节点，可以减少上电时的通过电流。

公开(公告)号：US06819619B2

公开(公告)日：2004-11-16

申请号：US10356560

申请日：2003-02-03

申请人： Fukashi Morishita ,  Hiroshi Kato

发明人： Fukashi Morishita ,  Hiroshi Kato

IPC分类号： G11C514

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C5/147 ,  G11C2207/104

摘要： A semiconductor memory device includes a memory cell array, a data bus, a reference voltage generating circuit, a voltage down converter, a VPP generating circuit, a circuit group, and a test circuit. The reference voltage generating circuit, voltage down converter, and VPP generating circuit include thick film transistors having a gate oxide film thickness suitable to a power supply voltage of 3.3 V. Circuits included in the circuit group include thin film transistors having a gate oxide film thickness suitable to a power supply voltage of 1.5 V. The reference voltage generating circuit, voltage down converter, and VPP generating circuit including the thick film transistors are arranged to form units corresponding to the position of the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，数据总线，参考电压产生电路，降压转换器，VPP生成电路，电路组和测试电路。 参考电压产生电路，降压转换器和VPP产生电路包括具有适合于3.3V的电源电压的栅极氧化膜厚度的厚膜晶体管。电路组中包括的电路包括具有栅氧化物膜厚度 适合于1.5V的电源电压。包括厚膜晶体管的参考电压产生电路，降压转换器和VPP产生电路被布置成形成与存储单元阵列的位置对应的单元。

公开(公告)号：US20100231768A1

公开(公告)日：2010-09-16

申请号：US12722121

申请日：2010-03-11

申请人： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

发明人： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

IPC分类号： H04N5/335

CPC分类号： H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

摘要： There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

摘要翻译： 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US08736732B2

公开(公告)日：2014-05-27

申请号：US12722121

申请日：2010-03-11

申请人： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

发明人： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

IPC分类号： H04N5/335

CPC分类号： H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

摘要： There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

摘要翻译： 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US20100033609A1

公开(公告)日：2010-02-11

申请号：US12473876

申请日：2009-05-28

申请人： Hiroshi KATO ,  Katsumi Dosaka ,  Fukashi Morishita

发明人： Hiroshi KATO ,  Katsumi Dosaka ,  Fukashi Morishita

IPC分类号： H04N5/335

CPC分类号： H04N5/3742 ,  H04N5/378

摘要： To obtain a solid state imaging device having a data transfer function capable of outputting digital data after A/D conversion to the outside in a high speed.Each of eight stage data blocks in a data bus part has a data line pair and an amplifier part which is coupled to the data line pair. Then, the amplifier part amplifies a signal of the data line pair on an amplifier data line pair to output the amplified signal as block data outputs at timing indicated by an amplifier enable signal and an amplifier control signal. Further, the eight stage data blocks are coupled with each other from the first stage to the last stage so that the preceding stage block data outputs may be provided to the following stage data line pair as block data inputs, respectively.

摘要翻译： 获得具有数据传送功能的固态成像装置，该数据传输功能能够在高速A / D转换到外部之后输出数字数据。 数据总线部分中的八级数据块中的每一个具有数据线对和耦合到数据线对的放大器部分。 然后，放大器部分放大放大器数据线对上的数据线对的信号，以在由放大器使能信号和放大器控制信号指示的定时处输出放大信号作为块数据输出。 此外，八级数据块从第一级到最后级彼此耦合，使得前级级块数据输出可以分别作为块数据输入提供给后级数据线对。

公开(公告)号：US08638583B2

公开(公告)日：2014-01-28

申请号：US13621078

申请日：2012-09-15

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US08154271B2

公开(公告)日：2012-04-10

申请号：US13115327

申请日：2011-05-25

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： G05F3/16

CPC分类号： G05F1/465

摘要： The semiconductor integrated circuit device includes load circuits and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. The regulator circuit is formed over an SOI substrate and includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a main amplifier circuit for amplifying the output of the preamplifier circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal. An input stage of the main amplifier circuit is configured by MOS transistors coupling the gates and bodies of the MOS transistors.

摘要翻译： 半导体集成电路装置包括用于产生驱动负载电路的内部源电压的负载电路和内部电压发生器。 每个内部电压发生器包括用于产生参考电压的参考电压产生电路和用于参考参考电压产生内部源极电压的调节器电路。 调节器电路形成在SOI衬底上，并且包括用于检测和放大每个内部源电压和每个参考电压之间的差的前置放大器电路，用于放大前置放大器电路的输出并产生控制的主放大器电路 信号和用于响应于控制信号产生内部源电压的驱动器电路。 主放大器电路的输入级由耦合MOS晶体管的栅极和主体的MOS晶体管构成。

公开(公告)号：US20110221419A1

公开(公告)日：2011-09-15

申请号：US13115327

申请日：2011-05-25

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： G05F3/16

CPC分类号： G05F1/465

摘要： The semiconductor integrated circuit device includes load circuits and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. The regulator circuit is formed over an SOI substrate and includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a main amplifier circuit for amplifying the output of the preamplifier circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal. An input stage of the main amplifier circuit is configured by MOS transistors coupling the gates and bodies of the MOS transistors.

摘要翻译： 半导体集成电路装置包括用于产生驱动负载电路的内部源电压的负载电路和内部电压发生器。 每个内部电压发生器包括用于产生参考电压的参考电压产生电路和用于参考参考电压产生内部源极电压的调节器电路。 调节器电路形成在SOI衬底上，并且包括用于检测和放大每个内部源电压和每个参考电压之间的差的前置放大器电路，用于放大前置放大器电路的输出并产生控制的主放大器电路 信号和用于响应于控制信号产生内部源电压的驱动器电路。 主放大器电路的输入级由耦合MOS晶体管的栅极和主体的MOS晶体管构成。

公开(公告)号：US08004923B2

公开(公告)日：2011-08-23

申请号：US12683838

申请日：2010-01-07

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。