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    Sequence estimation method and sequence estimator
    1.
    发明授权
    Sequence estimation method and sequence estimator 失效

    公开(公告)号：US06996196B2

    公开(公告)日：2006-02-07

    申请号：US10315131

    申请日：2002-12-10

    申请人： Hiroshi Kubo ,  Kazuo Tanada ,  Keishi Murakami

    发明人： Hiroshi Kubo ,  Kazuo Tanada ,  Keishi Murakami

    IPC分类号： H04L27/06 ,  H03M13/03

    CPC分类号： H04L25/03191

    摘要： In a sequence estimation method and a sequence estimator of the present invention, a metric is calculated using a received signal and its estimated value, also another metric is calculated using a filtering result via a matching filter, one of these metrics is selected based on a characteristic of the channel or these metrics are combined, when a transmitted signal sequence transmitted from a transmission side is estimated based on a characteristic of a received signal and a channel using a list output Viterbi algorithm for deciding one or a plurality of survivors for each state of the Viterbi algorithm including one or more states. The operation speed and the characteristic of a channel can be improved using the smallest circuit scale even if the characteristic of a channel has a long delay time, in a sequence estimation method and a sequence estimator.

    Digital data demodulating device for estimating channel impulse response
    2.
    发明授权
    Digital data demodulating device for estimating channel impulse response 失效
    用于估计信道脉冲响应的数字数据解调装置

    公开(公告)号：US06219388B1

    公开(公告)日：2001-04-17

    申请号：US09007533

    申请日：1998-01-15

    申请人： Kazuo Tanada ,  Hiroshi Kubo ,  Keishi Murakami

    发明人： Kazuo Tanada ,  Hiroshi Kubo ,  Keishi Murakami

    IPC分类号： H03D100

    CPC分类号： H04L25/0212 ,  H04L25/03292

    摘要： A digital data demodulating device that estimates the channel impulse response (CIR) based on a received signal, and performs a viterbi algorithm using the replica generated according to the estimated CIR, and the received signal. The digital data demodulating device of the present invention follows the time variation of the channel by sequentially estimating the CIR in the CIR estimating circuit. The replica generating circuit of the digital data demodulating device includes a device for storing the estimated CIR and replica for each block therein, for reading the estimated CIR at a specific timing and updating the replica. A digital data demodulating device which reduce circuit scale, operates in a high speed, and appropriately follows the time variation of the channel, even in a high bit transmission rate and in a high delay dispersion of the multipass wave contained in the received signal.

    摘要翻译： 一种数字数据解调装置，其基于接收信号估计信道脉冲响应（CIR），并使用根据所估计的CIR产生的副本和所接收的信号执行维特比算法。 本发明的数字数据解调装置通过顺序估计CIR估计电路中的CIR，跟随信道的时间变化。 数字数据解调装置的复制品生成电路包括用于存储估计的CIR和用于每个块的副本的装置，用于在特定定时读取估计的CIR并更新副本。 即使在包含在接收信号中的多通道波的高位传输速率和高延迟色散中，数字数据解调装置降低电路规模，高速运行，并适当地跟随信道的时间变化。

    Sequence estimation method and sequence estimator
    3.
    发明授权
    Sequence estimation method and sequence estimator 失效
    序列估计方法和序列估计器

    公开(公告)号：US06556632B1

    公开(公告)日：2003-04-29

    申请号：US09083507

    申请日：1998-05-22

    申请人： Hiroshi Kubo ,  Kazuo Tanada ,  Keishi Murakami

    发明人： Hiroshi Kubo ,  Kazuo Tanada ,  Keishi Murakami

    IPC分类号： H04L2706

    CPC分类号： H04L25/03191

    摘要： In a sequence estimation method and a sequence estimator of the present invention, a metric is calculated using a received signal and its estimated value, also another metric is calculated using a filtering result via a matching filter, one of these metrics is selected based on a characteristic of the channel or these metrics are combined, when a transmitted signal sequence transmitted from a transmission side is estimated based on a characteristic of a received signal and a channel using a list output Viterbi algorithm for deciding one or a plurality of survivors for each state of the Viterbi algorithm including one or more states. The operation speed and the characteristic of a channel can be improved using the smallest circuit scale even if the characteristic of a channel has a long delay time, in a sequence estimation method and a sequence estimator.

    摘要翻译： 在本发明的序列估计方法和序列估计器中，使用接收信号及其估计值来计算度量，并且使用经过匹配滤波器的滤波结果来计算另一度量，这些度量之一是基于 当从发送侧发送的发送信号序列基于接收信号的特性和使用列表输出维特比算法的信道来估计每个状态的一个或多个幸存者时，将信道或这些度量的特征组合 维特比算法包括一个或多个状态。 在序列估计方法和序列估计器中，即使信道的特性具有较长的延迟时间，也可以使用最小的电路规模来提高信道的操作速度和特性。

    Method of sequence estimation
    4.
    发明授权
    Method of sequence estimation 有权
    序列估计方法

    公开(公告)号：US06314387B1

    公开(公告)日：2001-11-06

    申请号：US09171531

    申请日：1998-11-30

    申请人： Hiroshi Kubo ,  Keishi Murakami

    发明人： Hiroshi Kubo ,  Keishi Murakami

    IPC分类号： H01L2706

    CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H04L1/0054 ,  H04L1/006

    摘要： The prior art method of estimating a sequence by making use of a Viterbi algorithm is modified as follows: (1) A path at a certain past instant is modified to derive a modified path. (2) The path metric value of the modified path is calculated. (3) The path metric of a normal path and the path metric of the modified path are compared. If the path metric of the modified path is smaller, the path is modified. (4) A surviving path is selected from plural paths passing through the modified path.

    摘要翻译： 通过使用维特比算法估计序列的现有技术方法如下修改：（1）修改某一过去时刻的路径以导出修改的路径。 （2）计算修改路径的路径度量值。 （3）比较正常路径的路径度量和修改路径的路径度量。 如果修改路径的路径度量较小，则修改路径。 （4）从通过修改路径的多个路径中选择存活路径。

    Demodulator, clock recovery circuit, demodulation method and clock recovery method
    5.
    发明授权
    Demodulator, clock recovery circuit, demodulation method and clock recovery method 失效
    解调器，时钟恢复电路，解调方法和时钟恢复方法

    公开(公告)号：US06891906B1

    公开(公告)日：2005-05-10

    申请号：US09150011

    申请日：1998-09-09

    申请人： Yasushi Sogabe ,  Fumio Ishizu ,  Keishi Murakami

    发明人： Yasushi Sogabe ,  Fumio Ishizu ,  Keishi Murakami

    IPC分类号： H03M5/12 ,  H04L7/027 ,  H04L25/49 ,  H03D1/00

    CPC分类号： H03M5/12

    摘要： A demodulator is constituted by: a clock recovery circuit for generating a recovered clock from the series of received data and outputting the recovered clock; a state estimation circuit for making an estimation about a reception state such as waveform distortion or the like from the series of received data, and outputting waveform information based on the result of the estimation; and a correlator for correcting a reference and/or sample points on the basis of the recovered clock and the waveform information, obtaining a correlation value between the series of received data and the reference from a plurality of the sample points, and outputting demodulated data on the basis of the correlation value.

    摘要翻译： 解调器由以下部件构成：时钟恢复电路，用于从所述一系列接收数据产生恢复的时钟并输出恢复时钟; 状态估计电路，用于从所述一系列接收数据中对诸如波形失真等的接收状态进行估计，并且基于所述估计结果来输出波形信息; 以及相关器，用于基于恢复的时钟和波形信息来校正参考和/或采样点，从多个采样点获得所接收的数据序列与参考之间的相关值，并且输出解调数据 相关值的基础。

    Equalizer
    6.
    发明授权
    Equalizer 失效
    均衡器

    公开(公告)号：US5175747A

    公开(公告)日：1992-12-29

    申请号：US730675

    申请日：1991-07-16

    申请人： Keishi Murakami

    发明人： Keishi Murakami

    IPC分类号： H04L25/03

    CPC分类号： H04L25/03057

    摘要： An adaptive equalizer comprising a computing unit which receives a known signal sequence to estimate transmission channel characteristics and effect compensatory control of tap coefficients by use of a first algorithm that has fast convergence property, and a tap coefficient computing unit for making compensation for relatively slow changes in a random data input after the compensation for the transmission channel characteristics, which either employs an algorithm that involves a relatively low computational complexity or intermittently executes computation which contains an interpolation of consecutive sets of tap coefficients between intermittent intervals.

    摘要翻译： 一种自适应均衡器，包括计算单元，其接收已知信号序列以估计传输信道特性，并通过使用具有快速收敛特性的第一算法来实现抽头系数的补偿控制;以及抽头系数计算单元，用于对相对缓慢的变化进行补偿 在补偿传输信道特性之后的随机数据输入中，其采用涉及相对低的计算复杂度的算法或间歇地执行包含间歇间隔之间的连续抽头系数组的插值的计算。

    Equalizer
    10.
    发明授权
    Equalizer 失效
    均衡器

    公开(公告)号：US5068873A

    公开(公告)日：1991-11-26

    申请号：US604940

    申请日：1990-10-29

    申请人： Keishi Murakami

    发明人： Keishi Murakami

    IPC分类号： H04L25/03

    CPC分类号： H04L25/03057

    摘要： "An adaptive equalizer comprising a computer unit which receives a known signals sequence to estimate transmission channel characteristics and effect compensatory control of tap coefficients by use of a first algorithm that has fast convergence property, and a tap coefficient computing unit for making compensation for relatively slow changes in a random data input after the compensation for the transmission channel characteristics, which either employs an algorithm that involves a relatively low computational complexity or intermittently executes computation."