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公开(公告)号：US20120105679A1
公开(公告)日：2012-05-03
申请号：US13274324
申请日：2011-10-15
CPC分类号： G06T5/006 , G06T2200/28 , G06T2207/10004 , H04N5/2173 , H04N5/23238 , H04N5/247 , H04N5/357 , H04N5/3572 , H04N5/77 , H04N5/907
摘要： The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.
摘要翻译： 提供本发明以在将由多个摄像机捕获的图像数据存储到半导体存储器的情况下减少总线上的负载。 对于半导体集成电路，可以耦合多个摄像机和半导体存储器。 半导体集成电路包括多个第一接口，第二接口，总线和多个图像处理模块。 图像处理模块包括对预先指定区域中的图像数据进行失真校正的处理，并且经过失真校正的区域中的图像数据经由总线和第二接口写入半导体存储器。 通过从图像处理模块中的失真校正对象中排除预先指定区域之外的图像数据，减少了传送到半导体存储器的图像数据量。
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公开(公告)号：US09071750B2
公开(公告)日：2015-06-30
申请号：US13274324
申请日：2011-10-15
CPC分类号： G06T5/006 , G06T2200/28 , G06T2207/10004 , H04N5/2173 , H04N5/23238 , H04N5/247 , H04N5/357 , H04N5/3572 , H04N5/77 , H04N5/907
摘要： The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.
摘要翻译： 提供本发明以在将由多个摄像机捕获的图像数据存储到半导体存储器的情况下减少总线上的负载。 对于半导体集成电路，可以耦合多个摄像机和半导体存储器。 半导体集成电路包括多个第一接口，第二接口，总线和多个图像处理模块。 图像处理模块包括对预先指定区域中的图像数据进行失真校正的处理，并且经过失真校正的区域中的图像数据经由总线和第二接口写入半导体存储器。 通过从图像处理模块中的失真校正对象中排除预先指定区域之外的图像数据，减少了传送到半导体存储器的图像数据量。
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公开(公告)号：US20090049325A1
公开(公告)日：2009-02-19
申请号：US12135189
申请日：2008-06-08
IPC分类号： G06F1/04
摘要： It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.
摘要翻译： 旨在提供一种能够从同步时钟的角度抑制突发电流变化的数据处理器。 数据处理器1包括时钟脉冲产生电路和对从时钟脉冲发生电路输出的输入时钟信号CLKi进行操作的电路模块。 在从上电复位期间或待机状态恢复的情况下，时钟脉冲发生电路逐步地将时钟信号的频率从低频变为高频。 这使得可以防止在从上电复位周期或待机状态恢复的情况下电源电流突然增加。
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公开(公告)号：US20050268130A1
公开(公告)日：2005-12-01
申请号：US11130218
申请日：2005-05-17
摘要： It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.
摘要翻译： 旨在提供一种能够从同步时钟的角度抑制突发电流变化的数据处理器。 数据处理器1包括时钟脉冲产生电路和对从时钟脉冲发生电路输出的输入时钟信号CLKi进行操作的电路模块。 在从上电复位期间或待机状态恢复的情况下，时钟脉冲发生电路逐步地将时钟信号的频率从低频变为高频。 这使得可以防止在从上电复位周期或待机状态恢复的情况下电源电流突然增加。
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公开(公告)号：US07398406B2
公开(公告)日：2008-07-08
申请号：US11130218
申请日：2005-05-17
摘要： It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.
摘要翻译： 旨在提供一种能够从同步时钟的角度抑制突发电流变化的数据处理器。 数据处理器1包括时钟脉冲产生电路和对从时钟脉冲发生电路输出的输入时钟信号CLKi进行操作的电路模块。 在从上电复位期间或待机状态恢复的情况下，时钟脉冲发生电路逐步地将时钟信号的频率从低频变为高频。 这使得可以防止在从上电复位周期或待机状态恢复的情况下电源电流突然增加。
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