公开(公告)号：US06388941B2

公开(公告)日：2002-05-14

申请号：US09903509

申请日：2001-07-13

申请人： Hiroshi Otori ,  Hiroki Fujisawa ,  Minoru Ebihara ,  Seiji Narui ,  Masanori Isoda ,  Akira Ohta

发明人： Hiroshi Otori ,  Hiroki Fujisawa ,  Minoru Ebihara ,  Seiji Narui ,  Masanori Isoda ,  Akira Ohta

IPC分类号： G11C800

CPC分类号： G11C29/70 ,  G11C5/025 ,  G11C5/063

摘要： Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.

摘要翻译： 每个具有用于根据阈值电压差存储信息的可电气可编程电保险丝和地址比较器的排气单元（UNITb）设置在第二区域中，并且每个具有激光熔丝和地址比较器的释放单元（UNITa）设置在 第一个区域。 两个区域沿着每个比较器的地址信号布线彼此相邻，并且地址信号布线线性布置。 即使电保险丝和激光熔丝被共存用于释放地址存储，也可以基于在地址信号布线的方向上延伸的大小来调整由于它们的配置之间的差异造成的片外占用面积之间的差异， 并且可以从布局的观点最大限度地抑制片上占用面积的增加。

公开(公告)号：US06563750B2

公开(公告)日：2003-05-13

申请号：US10134521

申请日：2002-04-30

申请人： Hiroshi Otori ,  Hiroki Fujisawa ,  Minoru Ebihara ,  Seiji Narui ,  Masanori Isoda ,  Akira Ohta

发明人： Hiroshi Otori ,  Hiroki Fujisawa ,  Minoru Ebihara ,  Seiji Narui ,  Masanori Isoda ,  Akira Ohta

IPC分类号： G11C700

CPC分类号： G11C29/70 ,  G11C5/025 ,  G11C5/063

摘要： Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.

摘要翻译： 每个具有用于根据阈值电压差存储信息的电可编程电保险丝和地址比较器的排气单元（UNITb）设置在第二区域中，并且每个具有激光熔丝和地址比较器的释放单元（UNITa）设置在 第一个区域。 两个区域沿着每个比较器的地址信号布线彼此相邻，并且地址信号布线线性布置。 即使电保险丝和激光熔丝被共存用于释放地址存储，也可以基于在地址信号布线的方向上延伸的大小来调整由于它们的配置之间的差异造成的片外占用面积之间的差异， 并且可以从布局的观点最大限度地抑制片上占用面积的增加。

公开(公告)号：US06847580B2

公开(公告)日：2005-01-25

申请号：US10282810

申请日：2002-10-29

申请人： Minoru Ebihara ,  Tsugio Takahashi ,  Hiroshi Watanabe

发明人： Minoru Ebihara ,  Tsugio Takahashi ,  Hiroshi Watanabe

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/12 ,  G11C11/407 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C8/12 ,  G11C11/4087

摘要： A method for controlling reading data that can increase the data transfer rate in an SDRAM of a posted CAS standard. A memory cell array is constituted by two sub-arrays that can be independently activated. When a READ command is received as an input one clock cycle after the input of an ACTV command, a row decoder activates only the sub-array containing the memory cell that is selected by a row address AX and column address AY, and then carries out the operations for reading data. The present invention thus reduces the areas that must be activated, thereby decreasing the load on the power supply and, when amplifying bit lines, shortening the time for the voltage of bit lines to attain the stipulated voltage. Consequently, the present invention increases the speed of reading data.

摘要翻译： 一种用于控制可以增加已发布的CAS标准的SDRAM中的数据传输速率的读取数据的方法。 存储单元阵列由可独立激活的两个子阵列构成。 当在ACTV命令的输入之后一个时钟周期接收到READ命令作为输入时，行解码器仅激活包含由行地址AX和列地址AY选择的存储单元的子阵列，然后执行 读取数据的操作。 因此，本发明减少必须被激活的区域，从而减小电源上的负载，并且当放大位线时，缩短位线电压的时间以达到规定的电压。 因此，本发明增加了读取数据的速度。