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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5699311A

    公开(公告)日：1997-12-16

    申请号：US763667

    申请日：1996-12-11

    申请人： Hiroshi Sato ,  Keiichi Yoshida ,  Tetsuya Tsujikawa

    发明人： Hiroshi Sato ,  Keiichi Yoshida ,  Tetsuya Tsujikawa

    IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/06 ,  G11C16/00 ,  G11C16/06 ,  G11C16/26 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C8/04

    CPC分类号： G11C7/00 ,  G11C16/26 ,  G11C7/06

    摘要： A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.

    摘要翻译： 一种半导体存储器件，其中包括存储晶体管的多条数据线被包括存储晶体管，按存储数据排列成具有高阈值电压或低阈值电压的矩阵形式，被分成多个块，以及读出放大器用于进行放大 时间分散的操作用于放大信号。 此外，布置与奇数和偶数编号的相邻数据线相对应的第一组和第二组读出放大器，以便输出一组读出放大器的输出信号，切换字线，另一组感测 导致放大器分别执行放大从与这样切换的字线对应的存储单元读出的信号的操作。

    Semiconductor memory device having an improved sense amplifier arrangement
    2.
    发明授权
    Semiconductor memory device having an improved sense amplifier arrangement 失效
    具有改进的读出放大器布置的半导体存储器件

    公开(公告)号：US5654916A

    公开(公告)日：1997-08-05

    申请号：US510465

    申请日：1995-08-02

    申请人： Hiroshi Sato ,  Keiichi Yoshida ,  Tetsuya Tsujikawa

    发明人： Hiroshi Sato ,  Keiichi Yoshida ,  Tetsuya Tsujikawa

    IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/06 ,  G11C16/00 ,  G11C16/06 ,  G11C16/26 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C7/00 ,  G11C16/26 ,  G11C7/06

    摘要： A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.

    摘要翻译： 一种半导体存储器件，其中包括存储晶体管的多条数据线被包括存储晶体管，按存储数据排列成具有高阈值电压或低阈值电压的矩阵形式，被分成多个块，以及读出放大器用于进行放大 时间分散的操作用于放大信号。 此外，布置与奇数和偶数编号的相邻数据线相对应的第一组和第二组读出放大器，以便输出一组读出放大器的输出信号，切换字线，另一组感测 导致放大器分别执行放大从与这样切换的字线对应的存储单元读出的信号的操作。

    Semiconductor memory device having an improved sense amplifier arrangement
    3.
    发明授权
    Semiconductor memory device having an improved sense amplifier arrangement 失效
    具有改进的读出放大器布置的半导体存储器件

    公开(公告)号：US5473570A

    公开(公告)日：1995-12-05

    申请号：US273170

    申请日：1994-07-26

    申请人： Hiroshi Sato ,  Keiichi Yoshida ,  Tetsuya Tsujikawa

    发明人： Hiroshi Sato ,  Keiichi Yoshida ,  Tetsuya Tsujikawa

    IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/06 ,  G11C16/00 ,  G11C16/06 ,  G11C16/26 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C7/00 ,  G11C16/26 ,  G11C7/06

    摘要： A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.

    摘要翻译： 一种半导体存储器件，其中包括存储晶体管的多条数据线被包括存储晶体管，按存储数据排列成具有高阈值电压或低阈值电压的矩阵形式，被分成多个块，以及读出放大器用于进行放大 时间分散的操作用于放大信号。 此外，布置与奇数和偶数编号的相邻数据线相对应的第一组和第二组读出放大器，以便输出一组读出放大器的输出信号，切换字线，另一组感测 导致放大器分别执行放大从与这样切换的字线对应的存储单元读出的信号的操作。

    Nonvolatile semiconductor storage device
    8.
    发明授权
    Nonvolatile semiconductor storage device 失效
    非易失性半导体存储器件

    公开(公告)号：US6166950A

    公开(公告)日：2000-12-26

    申请号：US117369

    申请日：1998-07-28

    申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

    发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

    IPC分类号： G11C11/56 ,  G11C11/34

    CPC分类号： G11C11/5628 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08

    摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

    摘要翻译： PCT No.PCT / JP96 / 01907 Sec。 371日期：1998年7月28日 102（e）1998年7月28日PCT PCT 1996年7月10日PCT公布。 公开号WO98 / 01861 日期1998年1月15日在其中设定多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，多位数据的位根据地址信号被单独写入存储单元， 一个控制信号来实现读取和擦除。 具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。