公开(公告)号：US20120133438A1

公开(公告)日：2012-05-31

申请号：US13297639

申请日：2011-11-16

申请人： Hiroshi TSUCHI ,  Sensuke KIMURA

发明人： Hiroshi TSUCHI ,  Sensuke KIMURA

IPC分类号： H03F3/45

CPC分类号： H03F3/45219 ,  G09G3/20 ,  G09G2310/027 ,  G09G2310/0291

摘要： A differential amplifier has an interpolating function and has: first and second differential pairs including transistors of a first conductivity type; third and fourth differential pairs including transistors of a second conductivity type; first and second current sources providing operating currents to the first and second differential pairs; third and fourth current sources providing operating currents to the third and fourth differential pairs; a first control circuit which controls, in a first operating range where the amounts of currents flowing through the first and second differential pairs become smaller, respectively, a changing point at which the operating current of the first differential pair changes; and a second control circuit which controls, in a second operating range where the amounts of currents flowing through the third and fourth differential pairs become smaller, respectively, a changing point at which the operating current of the fourth differential pair changes.

摘要翻译： 差分放大器具有内插功能，并具有：第一和第二差分对，包括第一导电类型的晶体管; 第三和第四差分对，包括第二导电类型的晶体管; 第一和第二电流源向第一和第二差分对提供工作电流; 向第三和第四差分对提供工作电流的第三和第四电流源; 第一控制电路，其控制在第一工作范围内流过第一和第二差动对的电流量变小，第一差动对的工作电流变化的变化点; 以及第二控制电路，其在分别流过第三和第四差分对的电流量变小的第二工作范围内分别控制第四差分对的工作电流变化的变化点。

公开(公告)号：US20130088473A1

公开(公告)日：2013-04-11

申请号：US13612671

申请日：2012-09-12

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/00 ,  H03F3/45

CPC分类号： G09G3/3291 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2310/0291 ,  H03F3/3022 ,  H03F3/45076 ,  H03F3/45085 ,  H03F2200/153 ,  H03F2200/78 ,  H03F2203/45116 ,  H03F2203/45506 ,  H03F2203/45646 ,  H03F2203/45648 ,  H03F2203/45726

摘要： An output circuit is capable of supporting a high-speed operation, suppressing power consumption, and controlling its area. The output circuit has a differential input stage, an output amplification stage, and an amplification boost circuit, in which the amplification boost circuit has a differential pair of a second conductivity type and load element pair, and includes a first current source circuit for controlling current supply to an input node of a second current mirror circuit of the differential input stage and boost the charging operation of the output amplification stage according to a voltage difference between input and output voltages, and a second current source circuit for controlling current supply to an output node of a first current mirror circuit of the differential input stage and boost the discharging operation of the output amplification stage.

摘要翻译： 输出电路能够支持高速操作，抑制功耗，并控制其面积。 输出电路具有差分输入级，输出放大级和放大升压电路，其中放大升压电路具有第二导电类型和负载元件对的差分对，并且包括用于控制电流的第一电流源电路 提供给差分输入级的第二电流镜像电路的输入节点，并且根据输入和输出电压之间的电压差升高输出放大级的充电操作;以及第二电流源电路，用于控制对输出的电流供应 节点，并且对输出放大级的放电操作进行升压。

公开(公告)号：US20120146988A1

公开(公告)日：2012-06-14

申请号：US13304433

申请日：2011-11-25

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/00 ,  H03L5/00

CPC分类号： G09G3/3696 ,  G09G3/3258 ,  G09G5/00 ,  G09G2310/027 ,  G09G2310/0289 ,  H03K3/356165 ,  H03K19/0175

摘要： A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

摘要翻译： 电平移位电路包括分别耦合在第一电源端子和第一和第二输出节点之间的第一和第二NMOS晶体管，并且各自的控制端子接收低振幅，第三和第四PMOS晶体管的输入信号， 第二供电端子，以及分别输出高幅度信号的第一和第二输出节点，耦合在第三PMOS晶体管的栅极和第二输出节点之间的第五PMOS晶体管，并且具有耦合到第一输出端的栅极 节点，第六PMOS晶体管，其耦合在第四PMOS晶体管的栅极和第一输出节点之间，并且具有耦合到第二输出节点的栅极;以及耦合在第二供电端子和第二PMOS晶体管之间的第一和第二负载元件， 第三和第四PMOS晶体管的栅极。

公开(公告)号：US20110205218A1

公开(公告)日：2011-08-25

申请号：US13027450

申请日：2011-02-15

申请人： Hiroshi TSUCHI ,  Nobuyasu Doi

发明人： Hiroshi TSUCHI ,  Nobuyasu Doi

IPC分类号： G09G5/00 ,  H03K5/22

CPC分类号： G09G3/3688 ,  G09G3/3283 ,  G09G3/3291 ,  G09G2310/027

摘要： Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage. The first power supply voltage is a first reference voltage, which is a most spaced from the second voltage section among the first reference voltage group, or a predetermined voltage even further spaced from the second voltage section than the first reference voltage. The second power supply voltage is a predetermined voltage within a range from a second reference voltage, which is a voltage closest to the first voltage section among the second reference voltage group, to a voltage within the first voltage section but not reaching the first reference voltage.

摘要翻译： 公开了一种解码器，接收第一和第二参考电压组并根据接收到的数字信号选择参考电压，包括接收第一参考电压组的第一子解码器，接收第二参考电压的第二子解码器 并且第三子解码器接收由第二子解码器选择的参考电压，并将所选择的参考电压输出到解码器的第一子解码器或输出端。 第一子解码器包括具有提供有第一电源电压的背栅的第一导电类型的晶体管，第二子解码器包括具有提供有第二电源电压的背栅的第一导电类型的晶体管， 并且第三子解码器包括具有提供有第一电源电压的背栅的第一导电类型的晶体管。 第一电源电压是与第一参考电压组中的第二电压部分最多隔开的第一参考电压或者与第二电压部分比第一参考电压更远的预定电压。 第二电源电压是从第二参考电压组中最接近第一电压部分的电压的第二参考电压到第一电压部分内的电压但没有达到第一参考电压的范围内的预定电压 。

公开(公告)号：US20090244056A1

公开(公告)日：2009-10-01

申请号：US12385080

申请日：2009-03-30

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/00 ,  H03F3/45

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0291

摘要： Disclosed is an output amplifier circuit including a differential stage, a first output stage that receives outputs of the differential stage, and a second output stage having an output thereof electrically connected to a load. The differential stage receives an input signal at a non-inverting input thereof. In the first connection configuration, an output of the first output stage is electrically disconnected from the output of the second output stage, outputs of the differential stage are electrically disconnected from inputs of the second output stage, and a second input of the differential stage is electrically connected to the output of the first output stage. In the second connection configuration, the output of the first output stage is electrically connected to the output of the second output stage, and the outputs of the differential stage is electrically connected to the inputs of the second output stage.

摘要翻译： 公开了一种输出放大器电路，其包括差分级，接收差分级的输出的第一输出级和具有电连接到负载的输出的第二输出级。 差分级在其非反相输入端接收输入信号。 在第一连接结构中，第一输出级的输出与第二输出级的输出电断开，差动级的输出与第二输出级的输入电断开，差动级的第二输入为 电连接到第一输出级的输出端。 在第二连接结构中，第一输出级的输出电连接到第二输出级的输出，差分级的输出电连接到第二输出级的输入。

公开(公告)号：US20120200441A1

公开(公告)日：2012-08-09

申请号：US13447546

申请日：2012-04-16

申请人： Junichiro ISHII ,  Hiroshi TSUCHI

发明人： Junichiro ISHII ,  Hiroshi TSUCHI

IPC分类号： H03M1/66 ,  H01H47/00 ,  H02B1/24

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G2310/027 ,  Y10T307/74 ,  Y10T307/747

摘要： An output circuit includes a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.

摘要翻译： 输出电路包括连接开关和操作单元。 连接开关分别接收来自第一和第二端子的第一和第二电压，选择并输出第一至第三中间端子的第一电压或第二电压，包括选择相同的电压，并将第一和第二电压的分配切换到 响应于连接切换信号的第一到第三中间终端。 操作单元接收分配给第一至第三中间端子的电压，并向输出端子输出通过对电压执行预定操作而获得的电压。

公开(公告)号：US20110199366A1

公开(公告)日：2011-08-18

申请号：US13029888

申请日：2011-02-17

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0291 ,  G09G2320/0252 ,  G09G2330/021

摘要： Disclosed is an output circuit including a differential amplifier stage, an output amplifier stage, an amplification acceleration circuit and a capacitance connection control circuit. The output amplifier stage includes push/pull type transistors connected an output terminal. The amplification acceleration circuit includes a first switch and a first transistor, connected between a first output of the differential amplifier stage and the output terminal, and a second transistor and a second switch connected between the output terminal and a second output of the differential amplifier stage. The capacitance connection control circuit includes first capacitive element having first end connected to the output terminal, a first switch connected between a second end of the first capacitive element and a first voltage supply terminal, and a second switch connected between the second end of the first capacitive element and one output of a first differential pair of the differential amplifier stage.

摘要翻译： 公开了一种包括差分放大级，输出放大级，放大加速电路和电容连接控制电路的输出电路。 输出放大级包括连接有输出端的推/拉型晶体管。 放大加速电路包括连接在差分放大器级的第一输出端和输出端子之间的第一开关和第一晶体管，以及连接在差分放大器级的输出端子和第二输出端之间的第二晶体管和第二开关 。 电容连接控制电路包括第一电容元件，第一电容元件具有连接到输出端子的第一端子，连接在第一电容元件的第二端和第一电压供应端子之间的第一开关和连接在第一电容元件的第二端之间的第二开关 电容元件和差分放大器级的第一差分对的一个输出。

公开(公告)号：US20120306826A1

公开(公告)日：2012-12-06

申请号：US13477377

申请日：2012-05-22

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/00

CPC分类号： G09G3/006 ,  G09G3/2011 ,  G09G3/3291 ,  G09G3/3688 ,  G09G2300/043 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/12

摘要： A data driver for display panels includes: multiple driver output terminals coupled to multiple data lines of a display panel; and multiple output circuits that output output signals from the driver output terminals. Each output circuit includes: an output buffer that outputs an output signal; a first resistor having one end coupled to one of the driver output terminals; a first switch and a second resistor coupled in series between an output node of the output buffer and the other end of the first resistor; and a second switch coupled in parallel to the first switch and the second resistor between the output node of the output buffer and the other end of the first resistor.

摘要翻译： 用于显示面板的数据驱动器包括：耦合到显示面板的多个数据线的多个驱动器输出端子; 以及从驱动器输出端子输出输出信号的多个输出电路。 每个输出电路包括：输出缓冲器，输出一个输出信号; 第一电阻器，其一端耦合到所述驱动器输出端子之一; 串联耦合在输出缓冲器的输出节点和第一电阻器的另一端之间的第一开关和第二电阻器; 以及与输出缓冲器的输出节点和第一电阻器的另一端并联连接到第一开关和第二电阻器的第二开关。

公开(公告)号：US20110298777A1

公开(公告)日：2011-12-08

申请号：US13155023

申请日：2011-06-07

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G06F3/038

CPC分类号： G09G3/3275 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2310/0289

摘要： An output circuit includes a differential input stage, an output amplifier stage, a current control circuit; an input terminal, an output terminal. The current control circuit includes a first circuit that includes a second current source connected between a first power supply terminal and the second current mirror, and exercises control of switching between activating the second current source to couple a current from the second current source to a current on an input side of the first current mirror, and deactivating the second current source, depending on whether or not the input voltage is higher by more than a first preset value than the output voltage; and a second circuit that includes a third current source connected between the second power supply terminal and the first current mirror, and exercises control of switching between activating the third current source to couple a current from the third current source to a current on an input side of the second current mirror, and deactivating the third current source, depending on whether or not the input voltage is lower by more than a second preset value than the output voltage.

摘要翻译： 输出电路包括差分输入级，输出放大级，电流控制电路; 输入端子，输出端子。 电流控制电路包括第一电路，其包括连接在第一电源端子和第二电流镜之间的第二电流源，并且对激活第二电流源之间的切换进行控制以将来自第二电流源的电流耦合到电流 在第一电流镜的输入侧，根据输入电压是否高于比输出电压高的第一预设值，去激活第二电流源; 以及第二电路，其包括连接在第二电源端子和第一电流镜之间的第三电流源，并且在激活第三电流源之间进行切换控制以将来自第三电流源的电流耦合到输入侧的电流 并且根据输入电压是否低于输出电压的第二预设值来停用第三电流源。

公开(公告)号：US20110050746A1

公开(公告)日：2011-03-03

申请号：US12847339

申请日：2010-07-30

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/10 ,  H03L5/00

CPC分类号： G09G3/20 ,  G09G2310/027 ,  G09G2310/0289 ,  H03K19/018521

摘要： A level shift circuit includes a first circuit connected between a first power supply terminal (PST) and an output terminal (OT) of the level shift circuit to set OT to a first voltage (V1) when conducting, a second circuit connected between a second PST and OT to set OT to the second voltage (V2) when conducting, and a third circuit that receives an input signal and a feedback signal from OT so that, when OT=V2 and input=a third voltage (V3), the first circuit conducts, and when OT=V1, the first circuit is made nonconductive irrespective of the value of the input signal. The second circuit is made conductive and nonconductive, when the input=a fourth voltage (V4) and V3, respectively. A high/low relationship of V1, V2=that of V3, V4. The input between V3, V4 has a lower amplitude than the output signal between V1, V2.

摘要翻译： 电平移位电路包括连接在电平移位电路的第一电源端子（PST）和输出端子（OT）之间的第一电路，用于在导通时将OT设置为第一电压（V1），第二电路连接在第二电源 PST和OT将OT设置为第二电压（V2）;以及第三电路，其从OT接收输入信号和反馈信号，使得当OT = V2和输入=第三电压（V3）时，第一电路 电路导通，并且当OT = V1时，不管输入信号的值如何，第一电路都是不导通的。 当输入分别为第四电压（V4）和V3时，第二电路导通和不导通。 V1，V2的高低关系为V3，V4。 V3，V4之间的输入幅度比V1，V2之间的输出信号低。