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    Adaptive analog parallel combiner
    4.
    发明授权
    Adaptive analog parallel combiner 有权

    公开(公告)号：US11057065B1

    公开(公告)日：2021-07-06

    申请号：US16410545

    申请日：2019-05-13

    Applicant: Albert Vareljian ,  Vassili Kireev

    Inventor： Albert Vareljian ,  Vassili Kireev

    IPC: H04L27/08 ,  H04B1/10 ,  H04B1/16 ,  H03G3/20 ,  H03G5/16 ,  H03G5/00 ,  H03H17/00 ,  H03H15/00

    Abstract: An adaptive analog parallel combiner circuit for receiver data recovery from a communication signal is provided. The circuit includes a summer that sums outputs of a plurality of filter taps in parallel, including zeroth and first through Nth filter taps, each filter tap having as input the communication signal or a version thereof, wherein N is a finite integer greater than or equal to two. The zeroth filter tap has an amplifier with gain controlled by a zeroth adaptive gain control coefficient, and each of the first through Nth filter taps having an all pass filter and gain controlled amplification, with gain controlled by a corresponding one of a first through Nth adaptive gain control coefficients and the all pass filter implementing a transfer function having a zero and a pole equaling each other and at a base frequency divided by a corresponding integer from one through N.

    Digital equalizer for high-speed serial communications
    5.
    发明授权
    Digital equalizer for high-speed serial communications 有权
    数字均衡器，用于高速串行通信

    公开(公告)号：US08654898B2

    公开(公告)日：2014-02-18

    申请号：US12117515

    申请日：2008-05-08

    Applicant: William W. Bereza ,  Albert Vareljian ,  Rakesh H. Patel

    Inventor： William W. Bereza ,  Albert Vareljian ,  Rakesh H. Patel

    IPC: H04L27/01

    CPC classification number: H04L25/0272

    Abstract: Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.

    Abstract translation: 数字化高速串行接收机的传入数据，然后可以使用数字信号处理（DSP）技术来执行数字均衡。 这样的数字技术可以用于校正各种数据异常。 特别地，在可能涉及串扰的多通道系统中，其他通道的特性或甚至这些通道上的数据的知识可能允许减去串扰。 对数据通道几何的了解，特别是在背板传输的上下文中，可能允许减去连接器引起的回波和反射。 随着数据速率的提高，可以采用分数速率处理。 例如，可以以半速率执行模数转换，然后可以并行使用两个DSP，以在较高的初始时钟速率下维持吞吐量。 在更高的速率下，正交技术可以允许以四分之一速率进行模数转换，并行使用四个DSP。

    Echo cancellation for an ADSL modem
    7.
    发明授权
    Echo cancellation for an ADSL modem 有权
    ADSL调制解调器的回声消除

    公开(公告)号：US06480532B1

    公开(公告)日：2002-11-12

    申请号：US09352813

    申请日：1999-07-13

    Applicant: Albert Vareljian

    Inventor： Albert Vareljian

    IPC: H04L1200

    CPC classification number: H04B3/23

    Abstract: An echo cancellation functionality taps a digital transmit signal from a transmit channel for processing through an adaptive filter of an echo channel to generate an echo cancellation signal. The adaptive filter has a transfer function substantially matching an echo transfer function which defines a relationship between the transmit signal and an unwanted echo component corrupting an analog receive signal. The echo cancellation signal is digital-to-analog converted to an analog signal and then subtracted from the analog receive signal to substantially cancel out the unwanted echo component. The echo cancellation functionality may be configured in a training mode to generate an error signal used to adaptively configure the adaptive filter transfer function to substantially match the echo transfer function. When in training mode, certain components of an adaptation loop which contribute to a feedback loop transfer function are selectively by-passed. The adaptive filter may comprise a least mean square finite impulse response filter implementing a predistortion function to account for the feedback loop transfer function.

    Abstract translation: 回波消除功能从发送信道抽取数字发送信号，以便通过回波信道的自适应滤波器进行处理，以生成回声消除信号。 自适应滤波器具有基本上匹配回波传递函数的传递函数，该回波传递函数定义了发射信号与破坏模拟接收信号的不需要的回波分量之间的关系。 回波消除信号被数模转换成模拟信号，然后从模拟接收信号中减去，以基本上消除不需要的回波分量。 回波消除功能可以被配置在训练模式中以产生用于自适应地配置自适应滤波器传递函数以使得基本匹配回波传递函数的误差信号。 当处于训练模式时，选择性地绕过有助于反馈回路传递函数的适配回路的某些部件。 自适应滤波器可以包括实现预失真函数以解决反馈回路传递函数的最小均方有限脉冲响应滤波器。

    Full bridge decision feedback equalizer
    8.
    发明授权
    Full bridge decision feedback equalizer 有权

    公开(公告)号：US10164802B1

    公开(公告)日：2018-12-25

    申请号：US15345214

    申请日：2016-11-07

    Applicant: Albert Vareljian ,  Vassili Kireev

    Inventor： Albert Vareljian ,  Vassili Kireev

    IPC: H04L25/03

    Abstract: A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level.

    Adaptive analog parallel combiner
    10.
    发明授权
    Adaptive analog parallel combiner 有权

    公开(公告)号：US09853666B1

    公开(公告)日：2017-12-26

    申请号：US15345239

    申请日：2016-11-07

    Applicant: Albert Vareljian ,  Vassili Kireev

    Inventor： Albert Vareljian ,  Vassili Kireev

    IPC: H04L27/06 ,  H04B1/10 ,  H04B1/16 ,  H03G3/20

    CPC classification number: H03G5/005 ,  H03G5/16 ,  H03H15/00 ,  H03H15/023 ,  H03H17/00

    Abstract: An adaptive analog parallel combiner circuit for receiver data recovery from a communication signal is provided. The circuit includes a summer that sums outputs of a plurality of filter taps in parallel, including zeroth and first through Nth filter taps, each filter tap having as input the communication signal or a version thereof, wherein N is a finite integer greater than or equal to two. The zeroth filter tap has an amplifier with gain controlled by a zeroth adaptive gain control coefficient, and each of the first through Nth filter taps having an all pass filter and gain controlled amplification, with gain controlled by a corresponding one of a first through Nth adaptive gain control coefficients and the all pass filter implementing a transfer function having a zero and a pole equaling each other and at a base frequency divided by a corresponding integer from one through N.

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