公开(公告)号：US20150256360A1

公开(公告)日：2015-09-10

申请号：US14589872

申请日：2015-01-05

Applicant: Hiroshi Takatori ,  Albert Vareljian ,  Oleksiy Zabroda

Inventor： Hiroshi Takatori ,  Albert Vareljian ,  Oleksiy Zabroda

IPC: H04L25/03 ,  H04B3/32 ,  H03H21/00 ,  H04L1/00

CPC classification number: H04L25/03038 ,  H03H11/26 ,  H03H11/46 ,  H03H15/02 ,  H03H21/0001 ,  H04B3/32 ,  H04L1/0047 ,  H04L25/03057 ,  H04L25/03133 ,  H04L25/03343 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2025/03598

Abstract: According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.

Abstract translation: 根据本公开的实施例，通信发射机和接收机包括自适应滤波器和判决反馈均衡器以及串扰消除器。 自适应滤波器被配置为接收输入信号并且包括具有多个基于Padé的延迟元件的连续模拟延迟电路。

公开(公告)号：US08929429B2

公开(公告)日：2015-01-06

申请号：US12905912

申请日：2010-10-15

Applicant: Hiroshi Takatori ,  Albert Vareljian ,  Oleksiy Zabroda

Inventor： Hiroshi Takatori ,  Albert Vareljian ,  Oleksiy Zabroda

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H03H11/26 ,  H03H11/46 ,  H03H15/02

CPC classification number: H04L25/03038 ,  H03H11/26 ,  H03H11/46 ,  H03H15/02 ,  H03H21/0001 ,  H04B3/32 ,  H04L1/0047 ,  H04L25/03057 ,  H04L25/03133 ,  H04L25/03343 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2025/03598

Abstract: According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.

Abstract translation: 根据本公开的实施例，通信发射机和接收机包括自适应滤波器和判决反馈均衡器以及串扰消除器。 自适应滤波器被配置为接收输入信号并且包括具有多个基于Padé的延迟元件的连续模拟延迟电路。

公开(公告)号：US08766726B2

公开(公告)日：2014-07-01

申请号：US13572284

申请日：2012-08-10

Applicant: Oleksiy Zabroda

Inventor： Oleksiy Zabroda

IPC: H03F1/14

CPC classification number: H03F3/2176 ,  H03F1/14 ,  H03F3/45183 ,  H03F2203/45512

Abstract: An operational amplifier includes an operational amplifier circuit having at least one output node and an output stage coupled to the output node, the output stage containing an output and first MOS transistor employed in a common source amplifier mode, a frequency compensation capacitor coupled between the output of the output stage and the gate of the first transistor circuit by means of a second MOS transistor employed in a common gate amplifier mode. The other node of the capacitor and the output of the output stage are coupled to the amplifier output node with a resistor.

Abstract translation: 运算放大器包括具有至少一个输出节点和耦合到输出节点的输出级的运算放大器电路，该输出级包含以公共源放大器模式采用的输出和第一MOS晶体管，耦合在输出端之间的频率补偿电容器 和通过在公共栅极放大器模式中采用的第二MOS晶体管的第一晶体管电路的栅极。 电容器的另一个节点和输出级的输出端通过电阻耦合到放大器输出节点。

公开(公告)号：US20120139771A1

公开(公告)日：2012-06-07

申请号：US13166117

申请日：2011-06-22

Applicant: Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

IPC: H03M1/12

CPC classification number: H03M1/468

Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

Abstract translation: 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

公开(公告)号：US08704691B2

公开(公告)日：2014-04-22

申请号：US13607073

申请日：2012-09-07

Applicant: Oleksiy Zabroda

Inventor： Oleksiy Zabroda

IPC: H03M1/12

CPC classification number: G11C27/026

Abstract: A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter.

Abstract translation: 跟踪和保持电路至少包括第一和第二放大器级，以及耦合在第一和第二放大器级之间的开关电容器电路。 在跟踪和保持电路的轨道操作模式中，开关电容器电路被配置为将第二放大器级的输入与第一放大器级的相应输出分离，并将第二放大器级的输入耦合到公共 模式电压经由相应的第一和第二电容器。 在跟踪保持电路的保持操作模式中，开关电容器电路被配置为经由相应的第一和第二电容器将第二放大器级的输入耦合到第一放大器级的相应输出。 跟踪和保持电路的多个实例可以在时间交织的模数转换器中并行地实现。

公开(公告)号：US07015842B1

公开(公告)日：2006-03-21

申请号：US11033661

申请日：2005-01-12

Applicant: Sandeep Kumar Gupta ,  Oleksiy Zabroda

Inventor： Sandeep Kumar Gupta ,  Oleksiy Zabroda

IPC: H03M1/00

CPC classification number: G11C27/024 ,  H03M1/1215 ,  H03M1/1245

Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i−1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i−1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

公开(公告)号：US20050116743A1

公开(公告)日：2005-06-02

申请号：US10722544

申请日：2003-11-28

Applicant: Oleksiy Zabroda ,  David Nack

Inventor： Oleksiy Zabroda ,  David Nack

IPC: G05F1/10 ,  H03B1/00 ,  H03M1/08 ,  H03M1/74

CPC classification number: H03M1/0863 ,  H03M1/747

Abstract: An apparatus and method for a controlled current source are provided. The apparatus may include at least one current cell. Each current cell includes first, second and third transistors. The first transistor can be configured as a switch transistor. The second transistor can be configured as a current controller and can be coupled in series with the first transistor. The third transistor has a gate and a substrate coupled to a gate and a substrate of the second transistor, respectively. The drain and source of the third transistor can be coupled to a second input configured to receive a second signal that is a compliment of a first signal received at an input of the first transistor.

Abstract translation: 提供了一种用于受控电流源的装置和方法。 该装置可以包括至少一个当前小区。 每个当前单元包括第一，第二和第三晶体管。 第一晶体管可以配置为开关晶体管。 第二晶体管可以被配置为电流控制器并且可以与第一晶体管串联耦合。 第三晶体管分别具有与第二晶体管的栅极和衬底耦合的栅极和衬底。 第三晶体管的漏极和源极可以耦合到第二输入端，其被配置为接收第二信号，该第二信号是在第一晶体管的输入处接收到的第一信号的补充。

公开(公告)号：US20140070971A1

公开(公告)日：2014-03-13

申请号：US13607073

申请日：2012-09-07

Applicant: Oleksiy Zabroda

Inventor： Oleksiy Zabroda

IPC: G11C27/02 ,  H03M1/12

CPC classification number: G11C27/026

Abstract: A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter.

Abstract translation: 跟踪和保持电路至少包括第一和第二放大器级，以及耦合在第一和第二放大器级之间的开关电容器电路。 在跟踪和保持电路的轨道操作模式中，开关电容器电路被配置为将第二放大器级的输入与第一放大器级的相应输出分离，并将第二放大器级的输入耦合到公共 模式电压经由相应的第一和第二电容器。 在跟踪保持电路的保持操作模式中，开关电容器电路被配置为经由相应的第一和第二电容器将第二放大器级的输入耦合到第一放大器级的相应输出。 跟踪和保持电路的多个实例可以在时间交织的模数转换器中并行地实现。

公开(公告)号：US20140043100A1

公开(公告)日：2014-02-13

申请号：US13572284

申请日：2012-08-10

Applicant: Oleksiy Zabroda

Inventor： Oleksiy Zabroda

IPC: H03F3/16

CPC classification number: H03F3/2176 ,  H03F1/14 ,  H03F3/45183 ,  H03F2203/45512

Abstract: An operational amplifier includes an operational amplifier circuit having at least one output node and an output stage coupled to the output node, the output stage containing an output and first MOS transistor employed in a common source amplifier mode, a frequency compensation capacitor coupled between the output of the output stage and the gate of the first transistor circuit by means of a second MOS transistor employed in a common gate amplifier mode. The other node of the capacitor and the output of the output stage are coupled to the amplifier output node with a resistor.

Abstract translation: 运算放大器包括具有至少一个输出节点和耦合到输出节点的输出级的运算放大器电路，该输出级包含以公共源放大器模式采用的输出和第一MOS晶体管，耦合在输出端之间的频率补偿电容器 并且通过在公共栅极放大器模式中采用的第二MOS晶体管来控制第一晶体管电路的输出级和栅极。 电容器的另一个节点和输出级的输出端通过电阻耦合到放大器输出节点。

公开(公告)号：US20070127501A1

公开(公告)日：2007-06-07

申请号：US11655608

申请日：2007-01-19

Applicant: Oleksiy Zabroda

Inventor： Oleksiy Zabroda

IPC: H04L12/56 ,  H04L12/28

CPC classification number: H04L25/0292 ,  H04L12/413 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/028

Abstract: A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includes a plurality of transmitter cells consisting of a driver cell and digital to analog converter connected to driver cell. A hybrid circuit connects between the transmitter outputs and receiver inputs for separating a receiver signal from the transmitter signal responsive to a tuning signal. The hybrid circuit includes first and second resistor strings connected between the receiver inputs and the transmitter outputs, the first and second resistor strings each having many resistors with taps on each of the resistors; corresponding transistor switches connecting the taps of each of the first and second resistor strings to the hybrid inputs; and a circuit that selects a pair of the plurality of transistor switches connecting to a particular tap in response to the tuning signal such that a current to compensate for a transmitted signal is provided at the receiver inputs.

Abstract translation: 千兆以太网线路驱动器包括具有发射机和主动混合输出的发射机。 发射机由多个发射机簇组成，每个发射机簇都连接到发射机和主动混合输出。 每个发射机簇包括多个发射机小区，由发射机小区和连接到驱动小区的数模转换器组成。 混合电路连接在发射器输出端和接收器输入端之间，用于根据调谐信号将发射机信号与接收机信号分离。 混合电路包括连接在接收机输入端和发射机输出端之间的第一和第二电阻串，第一和第二电阻串各自具有许多电阻器，每个电阻器上都有抽头; 将所述第一和第二电阻串中的每一个的抽头连接到所述混合输入的对应的晶体管开关; 以及电路，其响应于调谐信号选择连接到特定抽头的一对多个晶体管开关，使得在接收器输入处提供补偿发送信号的电流。