公开(公告)号：US07756505B2

公开(公告)日：2010-07-13

申请号：US11240618

申请日：2005-10-03

申请人： Hiroshi Tanaka ,  Takanobu Tsunoda ,  Tetsuroo Honmura ,  Manabu Kawabe ,  Masashi Takada

发明人： Hiroshi Tanaka ,  Takanobu Tsunoda ,  Tetsuroo Honmura ,  Manabu Kawabe ,  Masashi Takada

IPC分类号： H04B1/28 ,  H04B1/26 ,  H04M3/00 ,  H04M1/00 ,  G06F7/38 ,  G06F15/00 ,  G06F15/76 ,  G06F9/00 ,  G06F9/44 ,  H03K19/173 ,  H03K19/177 ,  H01L27/10 ,  H01L29/76

CPC分类号： H04B1/0003 ,  H04B1/406

摘要： To realize a software radio processing with a reduced circuit area by hardware and software which can process transmission and reception, or synchronization and demodulation in time division. There are provided a circuit DRC that can dynamically change a configuration with a structure that can change the configuration at a high speed, a general processor, and an interface for connection with an external device such as an AD converter or a DA converter. Software radio is realized by using a software radio chip that conducts plural different processing such as transmission and reception, or synchronization and demodulation in time division. The different processing during the radio signal processing can be conducted in time division. As a result, the software radio can be realized with a circuit of a reduced area in a software radio system that allocates regions of an FPGA to the respective processing.

摘要翻译： 通过可以处理发送和接收的硬件和软件实现具有减少电路面积的软件无线电处理，或者在时间上进行同步和解调。 提供了一种电路DRC，其可以以可以以高速度改变配置的结构动态地改变配置，通用处理器以及用于与诸如AD转换器或DA转换器的外部设备连接的接口。 软件无线电通过使用进行多个不同处理的软件无线电芯片来实现，例如发送和接收，或者时分的同步和解调。 无线电信号处理期间的不同处理可以分时进行。 结果，软件无线电可以通过在分配FPGA的区域到相应处理的软件无线电系统中的减小区域的电路来实现。

公开(公告)号：US20060073804A1

公开(公告)日：2006-04-06

申请号：US11240618

申请日：2005-10-03

申请人： Hiroshi Tanaka ,  Takanobu Tsunoda ,  Tetsuroo Honmura ,  Manabu Kawabe ,  Masashi Takada

发明人： Hiroshi Tanaka ,  Takanobu Tsunoda ,  Tetsuroo Honmura ,  Manabu Kawabe ,  Masashi Takada

IPC分类号： H04B1/28

CPC分类号： H04B1/0003 ,  H04B1/406

摘要： To realize a software radio processing with a reduced circuit area by hardware and software which can process transmission and reception, or synchronization and demodulation in time division. There are provided a circuit DRC that can dynamically change a configuration with a structure that can change the configuration at a high speed, a general processor, and an interface for connection with an external device such as an AD converter or a DA converter. Software radio is realized by using a software radio chip that conducts plural different processing such as transmission and reception, or synchronization and demodulation in time division. The different processing during the radio signal processing can be conducted in time division. As a result, the software radio can be realized with a circuit of a reduced area in a software radio system that allocates regions of an FPGA to the respective processing.

摘要翻译： 通过可以处理发送和接收的硬件和软件实现具有减少电路面积的软件无线电处理，或者在时间上进行同步和解调。 提供了一种电路DRC，其可以以可以以高速度改变配置的结构动态地改变配置，通用处理器和用于与诸如AD转换器或DA转换器的外部设备连接的接口。 软件无线电通过使用进行多个不同处理的软件无线电芯片来实现，例如发送和接收，或者时分的同步和解调。 无线电信号处理期间的不同处理可以分时进行。 结果，软件无线电可以通过在分配FPGA的区域到相应处理的软件无线电系统中的减小区域的电路来实现。

公开(公告)号：US20060101232A1

公开(公告)日：2006-05-11

申请号：US11240549

申请日：2005-10-03

申请人： Masashi Takada ,  Takanobu Tsunoda ,  Hiroshi Tanaka ,  Tetsuroo Honmura

发明人： Masashi Takada ,  Takanobu Tsunoda ,  Hiroshi Tanaka ,  Tetsuroo Honmura

IPC分类号： G06F15/00

CPC分类号： G06F9/3879 ,  G06F15/7867

摘要： The present invention relates to data access to a built-in memory or a peripheral circuit from any of ALU cells provided in the array state, and provides a semiconductor integrated circuit having an access mechanism enabling size reduction in the hardware scale and improvement in the usability. There are provided dedicated cell groups 1304, 1306 for executing memory access processing to built-in memories 1313, 1312 in a plurality of ALU cells. Further there are provided dedicated cell groups 1304, 1306 enabling access commonly available for built-in memories to a peripheral circuit 1201 or LSI external device 206. By providing dedicated cell groups for memory access processing to built-in memories, the ALU cell does not require a memory access mechanism, which enables reduction of an area and improvement in efficiency in use. Further access common to the built-in memories or peripheral circuits is possible, which enables improvement in the usability.

摘要翻译： 本发明涉及从阵列状态中提供的任何一个ALU单元到内置存储器或外围电路的数据访问，并且提供了一种半导体集成电路，其具有能够缩小硬件尺寸并提高可用性的访问机构 。 提供了用于对多个ALU单元中的内置存储器1313,1312执行存储器访问处理的专用单元组1304,1306。 此外，还提供了专用单元组1304,1306，使外部电路1201或LSI外部设备206的内置存储器通用。通过为内置存储器提供用于存储器访问处理的专用单元组，ALU单元不 需要存储器访问机制，这使得能够减少面积并提高使用效率。 内置存储器或外围电路通用的进一步访问是可能的，这样可以改善可用性。

公开(公告)号：US20060190701A1

公开(公告)日：2006-08-24

申请号：US11271961

申请日：2005-11-14

申请人： Takanobu Tsunoda ,  Bryan Atwood ,  Masashi Takada ,  Hiroshi Tanaka

发明人： Takanobu Tsunoda ,  Bryan Atwood ,  Masashi Takada ,  Hiroshi Tanaka

IPC分类号： G06F15/00

CPC分类号： G06F15/16

摘要： There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.

摘要翻译： 提供至少一个处理器块，其包括多个加载存储接口（801,804），多个存储体（821），具有输入端口（850）和输出端口（850）中的至少一个的输入/输出端口 （860）和交叉开关（810），并且交叉开关将负载存储接口，存储体和输入/输出端口彼此连接，并且负载存储接口构成数据处理器，以便控制数据传送 到记忆库。 因此，实现了具有高传输吞吐量和灵活性并且有效地处理流数据的数据处理器。

公开(公告)号：US07765250B2

公开(公告)日：2010-07-27

申请号：US11271961

申请日：2005-11-14

申请人： Takanobu Tsunoda ,  Bryan Atwood ,  Masashi Takada ,  Hiroshi Tanaka

发明人： Takanobu Tsunoda ,  Bryan Atwood ,  Masashi Takada ,  Hiroshi Tanaka

IPC分类号： G06F7/38

CPC分类号： G06F15/16

摘要： There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.

摘要翻译： 提供至少一个处理器块，其包括多个加载存储接口（801,804），多个存储体（821），具有输入端口（850）和输出端口（850）中的至少一个的输入/输出端口 （860）和交叉开关（810），并且交叉开关将负载存储接口，存储体和输入/输出端口彼此连接，并且负载存储接口构成数据处理器，以便控制数据传送 到记忆库。 因此，实现了具有高传输吞吐量和灵活性并且有效地处理流数据的数据处理器。

公开(公告)号：US20060225139A1

公开(公告)日：2006-10-05

申请号：US11393833

申请日：2006-03-31

申请人： Masashi Takada ,  Takanobu Tsunoda ,  Hiroshi Tanaka

发明人： Masashi Takada ,  Takanobu Tsunoda ,  Hiroshi Tanaka

IPC分类号： H04L9/32 ,  G06F12/14 ,  G06F17/30 ,  G06F7/04 ,  G06F11/30 ,  G06K9/00 ,  H03M1/68 ,  H04K1/00 ,  H04L9/00 ,  H04N7/16

CPC分类号： G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： In a dynamic reconfigurable processor, a mechanism for effectively storing configuration data with a small hardware scale and improving processing performance is provided. Also, a sequence mechanism that is easy to be implemented with flexibility and a high operating frequency being both achieved is provided. The configuration data is hierarchically stored, and without suspending a process in a processing unit, configuration data required for subsequent processing is transferred in advance from a first storage area to a second storage area. Also, with a plurality of sequence modes, a condition determination process is performed on different sequence conditions.

摘要翻译： 在动态可重构处理器中，提供了用于有效地存储具有小硬件规模的配置数据并提高处理性能的机制。 此外，提供了容易实现的顺序机制，其灵活性和高操作频率都被实现。 配置数据被分层存储，并且在处理单元中不中止处理的情况下，将后续处理所需的配置数据预先从第一存储区域传送到第二存储区域。 此外，利用多个序列模式，对不同的序列条件执行条件确定处理。

公开(公告)号：US20070162529A1

公开(公告)日：2007-07-12

申请号：US11593542

申请日：2006-11-07

申请人： Makoto Sato ,  Takanobu Tsunoda ,  Masashi Takada

发明人： Makoto Sato ,  Takanobu Tsunoda ,  Masashi Takada

IPC分类号： G06J1/00

CPC分类号： G06F15/8007 ,  G06F15/7867

摘要： A dynamically reconfigurable processor having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area is provided. The dynamically reconfigurable processor comprises: a first arithmetic circuit group composed of arithmetic circuits of a type Ai (i=1, 2, . . . , N); a second arithmetic circuit group composed of a part of an arithmetic circuit group included in the first arithmetic circuit group and an arithmetic circuit group of a type B which is connected thereto and different from the arithmetic circuit of the type Ai; inter-arithmetic-circuit wires mutually connecting the arithmetic circuits of the type Ai and the arithmetic circuits of the type B; and a switch group which causes the inter-arithmetic-circuit wires in the second arithmetic circuit group to be inter-arithmetic-circuit wires different from other inter-arithmetic-circuit wires and changes the connection order between the arithmetic circuits in the second arithmetic circuit group.

摘要翻译： 提供一种具有布线结构的动态可重构处理器，其能够以小布线区域灵活地将程序映射到处理器。 该动态可重构处理器包括：由类型Ai（i = 1,2，...，N）的运算电路组成的第一运算电路组; 由第一运算电路组中包括的算术电路组的一部分和与该类型的运算电路不同的类型B的运算电路组组成的第二运算电路组; 将类型Ai的运算电路和B型运算电路相互连接的运算间电路布线; 以及使第二运算电路组中的运算电路布线之间的运算电路布线与其他算术电路布线不同的开关组，并且改变第二运算电路中的运算电路之间的连接顺序 组。

公开(公告)号：US07571198B2

公开(公告)日：2009-08-04

申请号：US11593542

申请日：2006-11-07

申请人： Makoto Sato ,  Takanobu Tsunoda ,  Masashi Takada

发明人： Makoto Sato ,  Takanobu Tsunoda ,  Masashi Takada

IPC分类号： G06F7/38

CPC分类号： G06F15/8007 ,  G06F15/7867

摘要： A dynamically reconfigurable processor is provided having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area. A first wire permits a first arrangement of circuit blocks and a second wire provided for changing the arrangement order of the circuit blocks. A switch is provided to switch between the first wire and the second wire. By virtue of this arrangement, a greater variety of calculations can be performed in the circuit without the necessity for increasing the number of operation blocks.

摘要翻译： 提供了具有布线结构的动态可重构处理器，其能够以小的布线区域灵活地将程序映射到处理器。 第一线允许电路块的第一布置和用于改变电路块的布置顺序的第二布线。 提供开关以在第一线和第二线之间切换。 通过这种布置，可以在电路中执行更多种类的计算，而不需要增加操作块的数量。

公开(公告)号：US20090320034A1

公开(公告)日：2009-12-24

申请号：US12280005

申请日：2006-03-27

申请人： Takanobu Tsunoda ,  Hiroshi Tanaka

发明人： Takanobu Tsunoda ,  Hiroshi Tanaka

IPC分类号： G06F9/46 ,  G06F12/00

CPC分类号： G11C7/1006 ,  G11C15/00 ,  G11C19/00

摘要： A data processing apparatus has a memory element array (330) having a plurality of entries each formed by a memory element of more than one bit having a data shift function and a data comparison function, and the memory element array is arranged so that data can be shifted between corresponding bit positions of adjacent entries. Further, the data processing apparatus has a priority-judging circuit (340) for identifying one of the entries according to predetermined priorities based on results of comparison between data input to the entries in common and contents held by the memory elements constituting the entries. Even when the data held by an entry located halfway is nullified, data shift between entries can avoid that the entry with nullified data remains halfway, and enables the entries to hold valid data in order with the data densely aligned. The time sequence when data are held can be made coincident with the alignment of entries readily. As the time sequence of the entries is ensured uniquely, a given data can be identified from CAM search results by factoring in the priorities following the time sequence.

摘要翻译： 一种数据处理装置具有存储元件阵列（330），其具有多个条目，每个条目由具有数据移位功能和数据比较功能的多于一个位的存储元件形成，并且存储元件阵列被布置成使得数据可以 在相邻条目的相应位位置之间移位。 此外，数据处理装置具有根据预先确定的优先顺序，根据输入到公共条目的数据和构成条目的存储元件所保持的内容之间的比较结果来识别条目之一的优先级判定电路（340）。 即使当一半条目所保存的数据无效时，条目之间的数据移动也可以避免具有无效数据的条目保持中途，并使条目能按照数据密集对齐的顺序保存有效数据。 保持数据的时间顺序可以与条目的对齐方式一致。 由于唯一地确保条目的时间顺序，可以通过考虑时间序列之后的优先级从CAM搜索结果来识别给定的数据。

公开(公告)号：US20090282213A1

公开(公告)日：2009-11-12

申请号：US12505128

申请日：2009-07-17

申请人： Hiroshi TANAKA ,  Yohei Akita ,  Tetsuro Honmura ,  Fumio Arakawa ,  Takanobu Tsunoda

发明人： Hiroshi TANAKA ,  Yohei Akita ,  Tetsuro Honmura ,  Fumio Arakawa ,  Takanobu Tsunoda

IPC分类号： G06F15/80 ,  G06F9/02

CPC分类号： H03K19/17752 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

摘要翻译： 能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。 该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径 切换OSW。 包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持 从多个数据输入节点中的任何一个输入的数据。