公开(公告)号：US07209260B1

公开(公告)日：2007-04-24

申请号：US09618537

申请日：2000-07-18

申请人： Hiroshi Tanaka ,  Yoshiyuki Nakai ,  Toru Adachi ,  Keiji Nakamura ,  Tokiyuki Okano ,  Kohsuke Harada

发明人： Hiroshi Tanaka ,  Yoshiyuki Nakai ,  Toru Adachi ,  Keiji Nakamura ,  Tokiyuki Okano ,  Kohsuke Harada

IPC分类号： G06K15/02

CPC分类号： H04N1/3935 ,  G06T1/60 ,  G06T3/40

摘要： The object of the present invention is to use the same FIFO line memory for both enlargement and reduction during variable-magnification processing in the scan direction, allowing reduction in circuit board area, reduction in power consumption, and reduction in cost, and to provide an image processing apparatus that allows variable-magnification processing to be carried out such that the speed of a scanning unit that captures image data during variable-magnification processing in the cross-scan direction is constant. During processing to enlarge an image in the scan direction, image data travels from CCD circuit board, passing through gate b of selector, is written to and read from FIFO memory, and from gate b of selector is written to memory provided at variable magnification unit. At variable magnification unit, image data is read from memory a plurality of times in correspondence to enlargement ratio, changing the magnification of the image data. Furthermore, image data is output through gate a of selector to LSU unit. During processing to reduce an image, image data travels from CCD circuit board, passing through gate a of selector, is input to variable magnification unit where it is subjected to variable-magnification processing, passes through gate a of selector, is written to and read from FIFO memory, passes through gate b of selector, and is output to LSU unit.

摘要翻译： 本发明的目的是在扫描方向的可变放大处理期间使用相同的FIFO行存储器进行放大和缩小，从而减少电路板面积，降低功耗并降低成本，并且提供 允许进行可变放大处理的图像处理装置，使得在横扫描方向的可变放大处理期间捕获图像数据的扫描单元的速度是恒定的。 在扫描方向放大图像的处理过程中，图像数据从CCD电路板行进，通过选择器的栅极b，被写入FIFO存储器并从FIFO存储器读取，并从选择器的栅极b写入可变倍率单位 。 在可变放大单元处，对应于放大率，从存储器多次读取图像数据，改变图像数据的放大率。 此外，图像数据通过选择器的门A输出到LSU单元。 在减少图像的处理过程中，图像数据从CCD电路板行进，通过选通器的门a，被输入到可变放大单元，经过可变放大处理，通过选通器的门a，被写入并读取 从FIFO存储器通过选择器的门b，并输出到LSU单元。

公开(公告)号：US20060209353A1

公开(公告)日：2006-09-21

申请号：US10552997

申请日：2004-04-08

申请人： Kohsuke Harada ,  Tokiyuki Okano ,  Keiji Nakamura ,  Takashi Nishimachi ,  Shuhji Fujii ,  Yasuhiro Nakai

发明人： Kohsuke Harada ,  Tokiyuki Okano ,  Keiji Nakamura ,  Takashi Nishimachi ,  Shuhji Fujii ,  Yasuhiro Nakai

IPC分类号： H04N1/00

CPC分类号： H04N1/32128 ,  H04N2201/0094 ,  H04N2201/3242 ,  H04N2201/3277

摘要： In an image processing apparatus connected with a computer which is capable of executing image processing which corresponds to an image processing command, a file format which permits addition of the image processing command to image data which has been read is stored in a non-volatile memory. A CPU judges whether a determined file format is stored in the non-volatile memory, and when judging that the determined file format is stored in the non-volatile memory, the CPU permits addition of the image processing command to the read image data.

摘要翻译： 在能够执行对应于图像处理命令的图像处理的计算机连接的图像处理装置中，允许将图像处理命令添加到已读取的图像数据的文件格式存储在非易失性存储器中 。 CPU判断所确定的文件格式是否存储在非易失性存储器中，并且当判断所确定的文件格式存储在非易失性存储器中时，CPU允许将图像处理命令添加到读取的图像数据。

公开(公告)号：US20060103889A1

公开(公告)日：2006-05-18

申请号：US11280584

申请日：2005-11-15

申请人： Toru Adachi ,  Kohsuke Harada ,  Hiroshi Tanaka

发明人： Toru Adachi ,  Kohsuke Harada ,  Hiroshi Tanaka

IPC分类号： H04N1/41

CPC分类号： H04N1/41 ,  H04N1/32486 ,  H04N2201/0091 ,  H04N2201/3297

摘要： An image forming one which is capable of shortening the first copy time and equalizing the image qualities of a plurality of all output copies when a plurality of copies of the original document are output using the memory copy function is provided. An image data of each one line of an original document is sequentially read by a scanner unit. Whenever the image data of a given portion of the original document less than one page thereof (for example, image data of 8 lines) is accumulated, it is subjected to irreversible compression in a compressing circuit. The irreversible compressed image data which is obtained by this irreversible compression is sequentially stored in a storage area of an image memory or HDD and thereafter is sequentially decompressed in a decompressing circuit. Image forming is sequentially conducted based upon the sequentially decompressed image data in a printing device.

摘要翻译： 提供了当使用存储器复制功能输出原始文档的多个副本时能够缩短第一复制时间并均衡多个全部输出副本的图像质量的图像。 原稿的每一行的图像数据被扫描器单元依次读取。 只要原始文档的给定部分的图像数据少于一页（例如，8行的图像数据）被累积，则在压缩电路中对其进行不可逆压缩。 将通过该不可逆压缩获得的不可逆压缩图像数据依次存储在图像存储器或HDD的存储区域中，然后在解压缩电路中依次解压缩。 基于打印装置中的顺序解压缩的图像数据顺序地进行图像形成。

公开(公告)号：US20070237405A1

公开(公告)日：2007-10-11

申请号：US11729779

申请日：2007-03-30

申请人： Kohsuke Harada ,  Tokiyuki Okano ,  Makoto Higuchi ,  Sohichi Takata

发明人： Kohsuke Harada ,  Tokiyuki Okano ,  Makoto Higuchi ,  Sohichi Takata

IPC分类号： G06K9/36

CPC分类号： H04N1/41

摘要： A storage area where compressed data is stored is divided into a plurality of divided areas having a data length of Ls. Each divided area is divided into two areas, a first area having a data length of Ld and a second area having a data length of La. A plurality of first areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed image data is composed. A plurality of second areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed attribute data is composed. Compressed image data is sequentially written starting from the upper address to the lower address of the memory area for compressed image data. Compressed attribute data is sequentially written starting from the upper address to the lower address of the memory area for compressed attribute data.

摘要翻译： 存储压缩数据的存储区域被划分成数据长度为Ls的多个划分区域。 每个划分区域被分成两个区域，数据长度为Ld的第一区域和数据长度为La的第二区域，多个第一区域从上部地址开始到下部地址，由此存储区域 为压缩图像数据组成。 从上部地址到下部地址收集多个第二区域，由此构成用于压缩属性数据的存储区域。 压缩图像数据从压缩图像数据的存储区域的上部地址到下部地址顺序写入。 压缩属性数据从压缩属性数据的存储区域的上部地址到下部地址顺序写入。

公开(公告)号：US07872766B2

公开(公告)日：2011-01-18

申请号：US11636019

申请日：2006-12-07

申请人： Makoto Higuchi ,  Kohsuke Harada ,  Tokiyuki Okano

发明人： Makoto Higuchi ,  Kohsuke Harada ,  Tokiyuki Okano

IPC分类号： G06F3/12 ,  G06K15/00 ,  B41J29/38

CPC分类号： G06K15/00 ,  G03G15/50

摘要： An FPGA functions as an activation mode setting circuit for loading activation data stored on a PROM into a circuit setting memory and setting an activation mode when activating the CPU. The FPGA outputs an activation mode setting signal to the CPU, and the CPU is activated in the set activation mode. After the CPU is activated, it follows predetermined processing steps, and performs a control operation to load the circuit setting data stored in a storage section into the circuit setting memory. Thus, the FPGA is constructed as a circuit having a desired function, and also constructed as an activation mode setting circuit when activating the CPU.

摘要翻译： FPGA用作激活模式设置电路，用于将存储在PROM上的激活数据加载到电路设置存储器中，并且在激活CPU时设置激活模式。 FPGA向CPU输出激活模式设置信号，CPU在设置激活模式下激活。 在CPU被激活之后，它遵循预定的处理步骤，并且执行控制操作以将存储在存储部分中的电路设置数据加载到电路设置存储器中。 因此，FPGA被构造为具有期望功能的电路，并且还在构造为激活CPU时的激活模式设置电路。

公开(公告)号：US07813565B2

公开(公告)日：2010-10-12

申请号：US11729779

申请日：2007-03-30

申请人： Kohsuke Harada ,  Tokiyuki Okano ,  Makoto Higuchi ,  Sohichi Takata

发明人： Kohsuke Harada ,  Tokiyuki Okano ,  Makoto Higuchi ,  Sohichi Takata

IPC分类号： G06K9/36 ,  G06K9/00 ,  G06K9/46

CPC分类号： H04N1/41

摘要： A storage area where compressed data is stored is divided into a plurality of divided areas having a data length of Ls. Each divided area is divided into two areas, a first area having a data length of Ld and a second area having a data length of La. A plurality of first areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed image data is composed. A plurality of second areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed attribute data is composed. Compressed image data is sequentially written starting from the upper address to the lower address of the memory area for compressed image data. Compressed attribute data is sequentially written starting from the upper address to the lower address of the memory area for compressed attribute data.

摘要翻译： 存储压缩数据的存储区域被划分成数据长度为Ls的多个划分区域。 每个划分区域被分成两个区域，数据长度为Ld的第一区域和数据长度为La的第二区域，多个第一区域从上部地址开始到下部地址，由此存储区域 为压缩图像数据组成。 从上部地址到下部地址收集多个第二区域，由此构成用于压缩属性数据的存储区域。 压缩图像数据从压缩图像数据的存储区域的上部地址到下部地址顺序写入。 压缩属性数据从压缩属性数据的存储区域的上部地址到下部地址顺序写入。

公开(公告)号：US20070146762A1

公开(公告)日：2007-06-28

申请号：US11636019

申请日：2006-12-07

申请人： Makoto Higuchi ,  Kohsuke Harada ,  Tokiyuki Okano

发明人： Makoto Higuchi ,  Kohsuke Harada ,  Tokiyuki Okano

IPC分类号： G06F3/12

CPC分类号： G06K15/00 ,  G03G15/50

摘要： An FPGA functions as an activation mode setting circuit for loading activation data stored on a PROM into a circuit setting memory and setting an activation mode when activating the CPU. The FPGA outputs an activation mode setting signal to the CPU, and the CPU is activated in the set activation mode. After the CPU is activated, it follows predetermined processing steps, and performs a control operation to load the circuit setting data stored in a storage section into the circuit setting memory. Thus, the FPGA is constructed as a circuit having a desired function, and also constructed as an activation mode setting circuit when activating the CPU.

摘要翻译： FPGA用作激活模式设置电路，用于将存储在PROM上的激活数据加载到电路设置存储器中，并且在激活CPU时设置激活模式。 FPGA向CPU输出激活模式设置信号，CPU在设置激活模式下激活。 在CPU被激活之后，它遵循预定的处理步骤，并且执行控制操作以将存储在存储部分中的电路设置数据加载到电路设置存储器中。 因此，FPGA被构造为具有期望功能的电路，并且还在构造为激活CPU时的激活模式设置电路。

公开(公告)号：US20070133065A1

公开(公告)日：2007-06-14

申请号：US11604801

申请日：2006-11-28

申请人： Tokiyuki Okano ,  Kohsuke Harada ,  Makoto Higuchi

发明人： Tokiyuki Okano ,  Kohsuke Harada ,  Makoto Higuchi

IPC分类号： H04N1/00

CPC分类号： H04N1/32561 ,  H04N1/00538 ,  H04N1/00928 ,  H04N1/0097 ,  H04N2201/0091

摘要： An image forming apparatus comprising an image processor which has output means for generating data for image formation based on image data and outputting the generated data for image formation and an image forming unit for forming an image based on the data for image formation generated by the image processor, wherein the image forming unit comprises storage means for storing information about an image forming speed and means for outputting the stored information, and the image processor comprises obtaining means for obtaining the information stored in the storage means and adjusting means for adjusting an output speed of the data for image formation based on the information obtained by the obtaining means.

摘要翻译： 一种图像形成装置，包括图像处理器，该图像处理器具有用于基于图像数据生成用于图像形成的数据的输出装置，并输出用于图像形成的所生成的数据和用于形成图像的图像形成单元， 处理器，其中所述图像形成单元包括用于存储关于图像形成速度的信息的存储装置和用于输出所存储的信息的装置，并且所述图像处理器包括获取装置，用于获得存储在存储装置中的信息和调整装置，用于调整输出速度 基于由获取装置获得的信息的图像形成数据。

公开(公告)号：US08077425B2

公开(公告)日：2011-12-13

申请号：US12542100

申请日：2009-08-17

申请人： Yasushi Tomizawa ,  Kohsuke Harada ,  Hiroaki Nakamura ,  Yoshiyuki Ishihara ,  Shinji Takakura

发明人： Yasushi Tomizawa ,  Kohsuke Harada ,  Hiroaki Nakamura ,  Yoshiyuki Ishihara ,  Shinji Takakura

IPC分类号： G11B21/02

CPC分类号： G11B5/82 ,  B82Y10/00 ,  G11B5/02 ,  G11B5/743 ,  G11B5/746 ,  G11B2005/0005

摘要： A magnetic disk apparatus includes a magnetic disk that includes a plurality of zones in which a plurality of tracks are arranged for each of circumferences of a spiral, and gaps that are arranged between the zones to have a width a predetermined number of times larger than a track width and that are regions without providing recording bits; and a reproducing element that simultaneously makes an access to the recording bits contained in the tracks, reading information stored in the recording bits, wherein the number of the tracks is one or larger and a sum of one and the predetermined number or smaller in one of the zones.

摘要翻译： 磁盘装置包括磁盘，该磁盘包括多个区域，其中为每个螺旋周期布置多个轨道，以及布置在该区域之间的间隙，其宽度大于一个 轨道宽度，并且是不提供记录位的区域; 以及再现元件，其同时访问包含在轨道中的记录位，读取存储在记录位中的信息，其中轨道的数量是一个或者更多，并且一个和一个和之和之和小于 区域。

公开(公告)号：US07979777B2

公开(公告)日：2011-07-12

申请号：US11723336

申请日：2007-03-19

申请人： Hironori Uchikawa ,  Kohsuke Harada

发明人： Hironori Uchikawa ,  Kohsuke Harada

IPC分类号： H03M13/00

CPC分类号： H03M13/114 ,  H03M13/616 ,  H03M13/6362

摘要： A decoder is configured to include an acquisition-unit configured to acquire first respective likelihoods of data-bits and second respective likelihoods of parity-bits. The data-bits and the parity-bits are included in code data obtained by LDPC-encoding the data-bits with a low density parity check matrix. The decoder also includes a detecting-unit configured to detect reliabilities of the first respective likelihoods and the second respective likelihoods. The decoder also includes a forming-unit configured to form an update schedule representing an order of updating the first and second respective likelihoods in order of increasing reliability, in accordance with the reliabilities. The decoder also includes an updating-unit configured to update the first and second respective likelihoods in the order represented by the update schedule, with the low density parity check matrix. The decoder also includes a discriminating-unit configured to execute hard decision of the likelihoods updated by the updating-unit. The decoder also includes a checking-unit configured to execute parity check of a discrimination result of the discriminating-unit, to obtain the code data.

摘要翻译： 解码器被配置为包括被配置为获取奇偶校验位的数据位和第二相应似然性的第一各自似然性的获取单元。 数据位和奇偶校验位包含在通过对具有低密度奇偶校验矩阵的数据位进行LDPC编码而获得的代码数据中。 解码器还包括被配置为检测第一各自的可能性和第二各自似然性的可靠性的检测单元。 解码器还包括形成单元，其被配置为根据可靠性形成表示更新第一和第二各个似然性的顺序的更新调度，以便增加可靠性。 解码器还包括更新单元，其被配置为利用低密度奇偶校验矩阵来以由更新调度表示的顺序来更新第一和第二各自的似然性。 解码器还包括被配置为执行由更新单元更新的可能性的硬判决的鉴别单元。 解码器还包括一个检查单元，被配置为执行鉴别单元的鉴别结果的奇偶校验，以获得代码数据。