Image processing apparatus
    2.
    发明授权
    Image processing apparatus 有权
    图像处理装置

    公开(公告)号:US07209260B1

    公开(公告)日:2007-04-24

    申请号:US09618537

    申请日:2000-07-18

    IPC分类号: G06K15/02

    CPC分类号: H04N1/3935 G06T1/60 G06T3/40

    摘要: The object of the present invention is to use the same FIFO line memory for both enlargement and reduction during variable-magnification processing in the scan direction, allowing reduction in circuit board area, reduction in power consumption, and reduction in cost, and to provide an image processing apparatus that allows variable-magnification processing to be carried out such that the speed of a scanning unit that captures image data during variable-magnification processing in the cross-scan direction is constant. During processing to enlarge an image in the scan direction, image data travels from CCD circuit board, passing through gate b of selector, is written to and read from FIFO memory, and from gate b of selector is written to memory provided at variable magnification unit. At variable magnification unit, image data is read from memory a plurality of times in correspondence to enlargement ratio, changing the magnification of the image data. Furthermore, image data is output through gate a of selector to LSU unit. During processing to reduce an image, image data travels from CCD circuit board, passing through gate a of selector, is input to variable magnification unit where it is subjected to variable-magnification processing, passes through gate a of selector, is written to and read from FIFO memory, passes through gate b of selector, and is output to LSU unit.

    摘要翻译: 本发明的目的是在扫描方向的可变放大处理期间使用相同的FIFO行存储器进行放大和缩小,从而减少电路板面积,降低功耗并降低成本,并且提供 允许进行可变放大处理的图像处理装置,使得在横扫描方向的可变放大处理期间捕获图像数据的扫描单元的速度是恒定的。 在扫描方向放大图像的处理过程中,图像数据从CCD电路板行进,通过选择器的栅极b,被写入FIFO存储器并从FIFO存储器读取,并从选择器的栅极b写入可变倍率单位 。 在可变放大单元处,对应于放大率,从存储器多次读取图像数据,改变图像数据的放大率。 此外,图像数据通过选择器的门A输出到LSU单元。 在减少图像的处理过程中,图像数据从CCD电路板行进,通过选通器的门a,被输入到可变放大单元,经过可变放大处理,通过选通器的门a,被写入并读取 从FIFO存储器通过选择器的门b,并输出到LSU单元。

    Image processing apparatus, image forming apparatus, and image processing method
    3.
    发明申请
    Image processing apparatus, image forming apparatus, and image processing method 有权
    图像处理装置,图像形成装置和图像处理方法

    公开(公告)号:US20070237405A1

    公开(公告)日:2007-10-11

    申请号:US11729779

    申请日:2007-03-30

    IPC分类号: G06K9/36

    CPC分类号: H04N1/41

    摘要: A storage area where compressed data is stored is divided into a plurality of divided areas having a data length of Ls. Each divided area is divided into two areas, a first area having a data length of Ld and a second area having a data length of La. A plurality of first areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed image data is composed. A plurality of second areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed attribute data is composed. Compressed image data is sequentially written starting from the upper address to the lower address of the memory area for compressed image data. Compressed attribute data is sequentially written starting from the upper address to the lower address of the memory area for compressed attribute data.

    摘要翻译: 存储压缩数据的存储区域被划分成数据长度为Ls的多个划分区域。 每个划分区域被分成两个区域,数据长度为Ld的第一区域和数据长度为La的第二区域,多个第一区域从上部地址开始到下部地址,由此存储区域 为压缩图像数据组成。 从上部地址到下部地址收集多个第二区域,由此构成用于压缩属性数据的存储区域。 压缩图像数据从压缩图像数据的存储区域的上部地址到下部地址顺序写入。 压缩属性数据从压缩属性数据的存储区域的上部地址到下部地址顺序写入。

    Image processing apparatus and image forming apparatus
    4.
    发明授权
    Image processing apparatus and image forming apparatus 有权
    图像处理装置和图像形成装置

    公开(公告)号:US07872766B2

    公开(公告)日:2011-01-18

    申请号:US11636019

    申请日:2006-12-07

    IPC分类号: G06F3/12 G06K15/00 B41J29/38

    CPC分类号: G06K15/00 G03G15/50

    摘要: An FPGA functions as an activation mode setting circuit for loading activation data stored on a PROM into a circuit setting memory and setting an activation mode when activating the CPU. The FPGA outputs an activation mode setting signal to the CPU, and the CPU is activated in the set activation mode. After the CPU is activated, it follows predetermined processing steps, and performs a control operation to load the circuit setting data stored in a storage section into the circuit setting memory. Thus, the FPGA is constructed as a circuit having a desired function, and also constructed as an activation mode setting circuit when activating the CPU.

    摘要翻译: FPGA用作激活模式设置电路,用于将存储在PROM上的激活数据加载到电路设置存储器中,并且在激活CPU时设置激活模式。 FPGA向CPU输出激活模式设置信号,CPU在设置激活模式下激活。 在CPU被激活之后,它遵循预定的处理步骤,并且执行控制操作以将存储在存储部分中的电路设置数据加载到电路设置存储器中。 因此,FPGA被构造为具有期望功能的电路,并且还在构造为激活CPU时的激活模式设置电路。

    Image processing apparatus, image forming apparatus, and image processing method
    5.
    发明授权
    Image processing apparatus, image forming apparatus, and image processing method 有权
    图像处理装置,图像形成装置和图像处理方法

    公开(公告)号:US07813565B2

    公开(公告)日:2010-10-12

    申请号:US11729779

    申请日:2007-03-30

    IPC分类号: G06K9/36 G06K9/00 G06K9/46

    CPC分类号: H04N1/41

    摘要: A storage area where compressed data is stored is divided into a plurality of divided areas having a data length of Ls. Each divided area is divided into two areas, a first area having a data length of Ld and a second area having a data length of La. A plurality of first areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed image data is composed. A plurality of second areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed attribute data is composed. Compressed image data is sequentially written starting from the upper address to the lower address of the memory area for compressed image data. Compressed attribute data is sequentially written starting from the upper address to the lower address of the memory area for compressed attribute data.

    摘要翻译: 存储压缩数据的存储区域被划分成数据长度为Ls的多个划分区域。 每个划分区域被分成两个区域,数据长度为Ld的第一区域和数据长度为La的第二区域,多个第一区域从上部地址开始到下部地址,由此存储区域 为压缩图像数据组成。 从上部地址到下部地址收集多个第二区域,由此构成用于压缩属性数据的存储区域。 压缩图像数据从压缩图像数据的存储区域的上部地址到下部地址顺序写入。 压缩属性数据从压缩属性数据的存储区域的上部地址到下部地址顺序写入。

    Image processing apparatus and image forming apparatus
    6.
    发明申请
    Image processing apparatus and image forming apparatus 有权
    图像处理装置和图像形成装置

    公开(公告)号:US20070146762A1

    公开(公告)日:2007-06-28

    申请号:US11636019

    申请日:2006-12-07

    IPC分类号: G06F3/12

    CPC分类号: G06K15/00 G03G15/50

    摘要: An FPGA functions as an activation mode setting circuit for loading activation data stored on a PROM into a circuit setting memory and setting an activation mode when activating the CPU. The FPGA outputs an activation mode setting signal to the CPU, and the CPU is activated in the set activation mode. After the CPU is activated, it follows predetermined processing steps, and performs a control operation to load the circuit setting data stored in a storage section into the circuit setting memory. Thus, the FPGA is constructed as a circuit having a desired function, and also constructed as an activation mode setting circuit when activating the CPU.

    摘要翻译: FPGA用作激活模式设置电路,用于将存储在PROM上的激活数据加载到电路设置存储器中,并且在激活CPU时设置激活模式。 FPGA向CPU输出激活模式设置信号,CPU在设置激活模式下激活。 在CPU被激活之后,它遵循预定的处理步骤,并且执行控制操作以将存储在存储部分中的电路设置数据加载到电路设置存储器中。 因此,FPGA被构造为具有期望功能的电路,并且还在构造为激活CPU时的激活模式设置电路。

    Image forming apparatus, image processing apparatus and image forming system
    7.
    发明申请
    Image forming apparatus, image processing apparatus and image forming system 审中-公开
    图像形成装置,图像处理装置和图像形成系统

    公开(公告)号:US20070133065A1

    公开(公告)日:2007-06-14

    申请号:US11604801

    申请日:2006-11-28

    IPC分类号: H04N1/00

    摘要: An image forming apparatus comprising an image processor which has output means for generating data for image formation based on image data and outputting the generated data for image formation and an image forming unit for forming an image based on the data for image formation generated by the image processor, wherein the image forming unit comprises storage means for storing information about an image forming speed and means for outputting the stored information, and the image processor comprises obtaining means for obtaining the information stored in the storage means and adjusting means for adjusting an output speed of the data for image formation based on the information obtained by the obtaining means.

    摘要翻译: 一种图像形成装置,包括图像处理器,该图像处理器具有用于基于图像数据生成用于图像形成的数据的输出装置,并输出用于图像形成的所生成的数据和用于形成图像的图像形成单元, 处理器,其中所述图像形成单元包括用于存储关于图像形成速度的信息的存储装置和用于输出所存储的信息的装置,并且所述图像处理器包括获取装置,用于获得存储在存储装置中的信息和调整装置,用于调整输出速度 基于由获取装置获得的信息的图像形成数据。

    Network system for copiers
    10.
    发明授权
    Network system for copiers 失效
    复印机网络系统

    公开(公告)号:US5915148A

    公开(公告)日:1999-06-22

    申请号:US99834

    申请日:1998-06-18

    摘要: A network system for copiers includes a plurality of copiers each provided with a communication device for communicating with external equipment and a power-on device for powering on the copier in a hold state in response to an external signal received by the communication device and a main controller including an operation controller for controlling operation of the copiers and a time setter for setting time to power on a copier, the main controller being connected to the copiers by a network. The operation controller executes control such that only predetermined one of the copiers is powered on at the power-on time set by the time setter.

    摘要翻译: 一种用于复印机的网络系统包括多个复印机,每个复印机具有用于与外部设备进行通信的通信设备和用于响应于由通信设备接收的外部信号而在保持状态下对复印机供电的上电设备,以及主设备 控制器包括用于控制复印机的操作的操作控制器和用于设置复印机上电时间的时间设定器,主控制器通过网络连接到复印机。 操作控制器执行控制,使得只有预定的一个复印机在由时间设定器设定的通电时间上通电。