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    Block erasable nonvolatile memory device
    1.
    发明授权
    Block erasable nonvolatile memory device 失效
    块可擦除非易失性存储器件

    公开(公告)号：US5371702A

    公开(公告)日：1994-12-06

    申请号：US27489

    申请日：1993-03-05

    申请人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano ,  Kazuhisa Kanazawa ,  Toshio Yamamura

    发明人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano ,  Kazuhisa Kanazawa ,  Toshio Yamamura

    IPC分类号： G11C16/16 ,  G11C11/34 ,  G11C7/00

    CPC分类号： G11C16/16

    摘要： In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks corresponding to the erase information holding sections in each of which the erase information data is held, so that a plurality of batch erase blocks can be erased simulataneously, thus reducing the erasure time, as compared with the prior art memory device.

    摘要翻译： 响应于从外部依次输入的多个地址信号，擦除信息输入部分控制与待擦除的批量擦除块相对应的擦除信息保持部分，以便保存擦除信息数据。 通过依次重复该操作，擦除信息数据被存储在与要擦除的多批擦除块相对应的擦除信息保持部分中。 接着，基于存储在擦除信息保持部中的擦除信息数据，块消除部分被激活，以擦除保持擦除信息数据的每个相应块的所有非易失性存储器单元。 结果，对于与保持擦除信息数据的擦除信息保持部分相对应的所有批量擦除块实现擦除操作，使得可以同时擦除多个批量擦除块，从而减少擦除 与现有技术的存储器件相比。

    Non-volatile semiconductor memory device using successively longer write pulses
    2.
    发明授权
    Non-volatile semiconductor memory device using successively longer write pulses 失效
    使用连续更长写入脉冲的非易失性半导体存储器件

    公开(公告)号：US5436913A

    公开(公告)日：1995-07-25

    申请号：US069911

    申请日：1993-06-01

    申请人： Toshio Yamamura ,  Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

    发明人： Toshio Yamamura ,  Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

    IPC分类号： G11C16/34 ,  G06F11/00

    CPC分类号： G11C16/3459 ,  G11C16/3454

    摘要： A non-volatile semiconductor memory device has writing part (203, 205, 209) for writing data in a non-volatile memory cell in response to a write pulse, readout part (419) for reading out data stored in the memory cell, and verification part (207, 210; 417) for verifying to ensure that normal writing has been completed by reading data from the memory cell after each writing. The device repeats writings unless a normal writing can be confirmed by the verification part. At this time, the writing part can vary writing time and in a part of a sequence of repeating writing unless a normal writing can be confirmed, it sets writing time longer for the next writing action than that for one writing action. Since this setting is performed according to constant multiplication, constant increment, or constant multiplication of accumulated value, necessary time for obtaining normal data write can be reduced.

    摘要翻译： 非挥发性半导体存储器件具有写入部分（203,205,209），用于响应写入脉冲在非易失性存储单元中写入数据，用于读出存储在存储器单元中的数据的读出部分（419）以及 验证部件（207,210; 417），用于通过在每次写入之后从存储器单元读取数据来验证以确保正常写入已经完成。 设备重复写入，除非验证部分可以确认正常写入。 此时，写入部分可以改变写入时间，并且在重复写入序列的一部分中，除非正常写入可以被确认，否则为下一个写入动作设置比一个写入动作的写入时间更长的时间。 由于根据常数乘法，常数增量或累积值的常数乘法执行该设置，因此可以减少获得正常数据写入所需的时间。