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22 条记录 (耗时 0.021 秒)

    Electrophotgraphic photosensitive member, process cartridge, and electrophotgraphic apparatus
    1.
    发明授权
    Electrophotgraphic photosensitive member, process cartridge, and electrophotgraphic apparatus 有权
    电光感光元件，处理盒和电子照相设备

    公开(公告)号：US06942952B2

    公开(公告)日：2005-09-13

    申请号：US10739346

    申请日：2003-12-19

    申请人： Hirotoshi Uesugi ,  Hideki Anayama ,  Itaru Yamazaki ,  Kazushige Nakamura ,  Akira Yoshida

    发明人： Hirotoshi Uesugi ,  Hideki Anayama ,  Itaru Yamazaki ,  Kazushige Nakamura ,  Akira Yoshida

    IPC分类号： G03G5/05 ,  G03G5/147 ,  G03G5/14

    CPC分类号： G03G5/0578 ,  G03G5/056 ,  G03G5/14747 ,  G03G5/14791 ,  G03G2215/0106 ,  G03G2215/0119 ,  G03G2215/0177 ,  G03G2221/183

    摘要： The present invention provides an electrophotographic photosensitive member capable of maintaining high transfer efficiency without causing large transfer current for a long-term use, obtaining an excellent image, and achieving those effects especially when being applied to a color electrophotographic apparatus. The invention also provides a process cartridge and an electrophotographic apparatus each having such a photosensitive member. The present invention includes an electrophotographic photosensitive member having a photosensitive layer on a support, a surface layer containing diorganopolysiloxane having specific repeating structure units α and β, and having a weight-average molecular weight of 1,000 to 1,000,000; in which a content of the diorganopolysiloxane in the surface layer is 0.01 to 20% by weight based on the entire weight of the surface layer (except in the case where the surface layer contains fluorine atom-containing resin particles).

    摘要翻译： 本发明提供了一种电子照相感光构件，其能够保持高的转印效率，而不会导致长期使用的大的转印电流，获得优异的图像，并且特别是当应用于彩色电子照相设备时实现这些效果。 本发明还提供了一种具有这种感光构件的处理盒和电子照相设备。 本发明包括在载体上具有感光层的电子照相感光构件，含有具有特定重复结构单元α和β的二有机聚硅氧烷，重均分子量为1,000至1,000,000的表面层; 表面层中的二有机聚硅氧烷的含量相对于表面层的整体重量为0.01〜20重量％（表面层含有含氟原子的树脂粒子的情况除外）。

    Processing apparatus
    9.
    发明授权
    Processing apparatus 失效
    处理装置

    公开(公告)号：US07937562B2

    公开(公告)日：2011-05-03

    申请号：US11190062

    申请日：2005-07-27

    申请人： Itaru Yamazaki ,  Tatsuo Teruyama

    发明人： Itaru Yamazaki ,  Tatsuo Teruyama

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3851

    摘要： A processing apparatus includes an execution stage which executes each of instruction streams, a first resource counter which counts the number of operating resources used when the execution stage executes a first one of the instruction streams, a second resource counter which holds data of the number of unused ones of the operating resources, and a control circuit which reads the count value of the first resource counter from a management table when a subsequent instruction stream is executed, to control a start of execution of the subsequent instruction stream in accordance with a subtraction result obtained by subtracting the count value from the data. The control circuit checks whether a number of operating resources required by the subsequent instruction stream is secured based on the subtraction result before the subsequent instruction stream starts to be executed.

    摘要翻译： 一种处理装置，包括执行各指令流的执行阶段，对执行阶段执行第一个指令流时所使用的操作资源的数量进行计数的第一资源计数器，保存数据的数据的第二资源计数器 未使用的操作资源，以及控制电路，当执行后续指令流时，从管理表读取第一资源计数器的计数值，以根据减法结果控制后续指令流的执行开始 通过从数据中减去计数值获得。 控制电路基于在后续指令流开始执行之前的减法结果来检查后续指令流所需的操作资源的数量是否得到确保。

    Circuit design apparatus, circuit design method, circuit design program and semiconductor integrated circuit fabrication method
    10.
    发明授权
    Circuit design apparatus, circuit design method, circuit design program and semiconductor integrated circuit fabrication method 失效
    电路设计装置，电路设计方法，电路设计程序和半导体集成电路制造方法

    公开(公告)号：US06543033B2

    公开(公告)日：2003-04-01

    申请号：US09816244

    申请日：2001-03-26

    申请人： Itaru Yamazaki ,  Nobuyuki Ikumi

    发明人： Itaru Yamazaki ,  Nobuyuki Ikumi

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068

    摘要： In a circuit design method, an arrangement/wiring section (112) determines an arrangement and wiring of logical blocks (40a, 40b, 40c, 40d) so that delay limitation information about input signals supplied to the logical blocks (40a, 40b, 40c, 40d) and limitation conditions about a difference of delay times among a pre-charge control signal (ck0, ck1, ck2) supplied to the corresponding logical lock (40a, 40b, 40c, 40d) and the input signals are satisfied.

    摘要翻译： 在电路设计方法中，布置/布线部分（112）确定逻辑块（40a，40b，40c，40d）的布置和布线，使得关于提供给逻辑块（40a，40b，40c）的输入信号的延迟限制信息 ，40d）和关于提供给相应逻辑锁（40a，40b，40c，40d）的预充电控制信号（ck0，ck1，ck2）与输入信号之间的延迟时间差的限制条件被满足。