利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

254 条记录 (耗时 0.043 秒)

    Non-volatile semiconductor storage device and method of manufacturing the same
    1.
    发明授权
    Non-volatile semiconductor storage device and method of manufacturing the same 有权
    非易失性半导体存储装置及其制造方法

    公开(公告)号：US08253187B2

    公开(公告)日：2012-08-28

    申请号：US12142289

    申请日：2008-06-19

    申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    IPC分类号： H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11556

    摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

    摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20080315296A1

    公开(公告)日：2008-12-25

    申请号：US12142289

    申请日：2008-06-19

    申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/115 ,  H01L27/11556

    摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

    摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20110284947A1

    公开(公告)日：2011-11-24

    申请号：US13198359

    申请日：2011-08-04

    申请人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

    发明人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

    摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

    摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

    Nonvolatile semiconductor memory device and manufacturing method thereof
    5.
    发明申请
    Nonvolatile semiconductor memory device and manufacturing method thereof 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20070252201A1

    公开(公告)日：2007-11-01

    申请号：US11654551

    申请日：2007-01-18

    申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

    发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

    摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

    摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

    Nonvolatile semicondutor memory device and manufacturing method thereof
    9.
    发明申请
    Nonvolatile semicondutor memory device and manufacturing method thereof 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20110287597A1

    公开(公告)日：2011-11-24

    申请号：US13064559

    申请日：2011-03-31

    申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

    发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

    摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

    摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

    Semiconductor memory device and manufacturing method thereof
    10.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US08659070B2

    公开(公告)日：2014-02-25

    申请号：US12561451

    申请日：2009-09-17

    申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

    发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7881 ,  H01L29/7926

    摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

    摘要翻译： 本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层 形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电 分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状 。