公开(公告)号：US20120313156A1

公开(公告)日：2012-12-13

申请号：US13592865

申请日：2012-08-23

申请人： Hiroyuki FUJIMOTO ,  Shinpei IIJIMA

发明人： Hiroyuki FUJIMOTO ,  Shinpei IIJIMA

IPC分类号： H01L27/06

CPC分类号： H01L27/10876 ,  H01L21/76897 ,  H01L27/10823 ,  H01L27/10855 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/861

摘要： A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.

摘要翻译： 形成半导体器件的方法包括以下处理。 在半导体衬底上形成立柱。 形成覆盖柱的侧面的第一绝缘膜。 去除第一绝缘膜的上部以暴露柱的上部的侧表面。 形成接触插塞，其接触柱的上部的侧表面和柱的顶表面。

公开(公告)号：US20110033994A1

公开(公告)日：2011-02-10

申请号：US12850092

申请日：2010-08-04

申请人： Hiroyuki FUJIMOTO ,  Shinpei IIJIMA

发明人： Hiroyuki FUJIMOTO ,  Shinpei IIJIMA

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L27/10876 ,  H01L21/76897 ,  H01L27/10823 ,  H01L27/10855 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/861

摘要： A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.

摘要翻译： 形成半导体器件的方法包括以下处理。 在半导体衬底上形成立柱。 形成覆盖柱的侧面的第一绝缘膜。 去除第一绝缘膜的上部以暴露柱的上部的侧表面。 形成接触插塞，其接触柱的上部的侧表面和柱的顶表面。

公开(公告)号：US20090197384A1

公开(公告)日：2009-08-06

申请号：US12423905

申请日：2009-04-15

申请人： Shinpei IIJIMA

发明人： Shinpei IIJIMA

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

摘要： According to an aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device is provided with an insulator and a capacitor. The capacitor is provided with a lower electrode provided with an inner portion and an outer portion, a dielectric portion on the lower electrode, and an upper electrode on the dielectric portion. The inner portion is provided with a lower part and an upper part upwardly extending from the lower part. The insulator laterally holds the lower part. The outer portion is arranged on the insulator and is electrically connected with the upper part.

摘要翻译： 根据本发明的一个方面，提供一种半导体存储器件。 半导体存储器件设置有绝缘体和电容器。 电容器设置有设置有内部部分和外部部分的下部电极，下部电极上的电介质部分和电介质部分上的上部电极。 内部具有从下部向上延伸的下部和上部。 绝缘体横向保持下部。 外部部分布置在绝缘体上并与上部电连接。

公开(公告)号：US20080296666A1

公开(公告)日：2008-12-04

申请号：US12132948

申请日：2008-06-04

申请人： Shinpei IIJIMA

发明人： Shinpei IIJIMA

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/0207 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

摘要： A semiconductor device includes an active area isolated by an isolation area on a semiconductor substrate. A transistor includes a gate electrode extending across the active area, source/drain regions formed in the active area on both sides of the gate electrode, and impurity-containing contact plugs connected to the source/drain regions. The source/drain regions are formed by thermal diffusion of impurities from the impurity-containing contact plugs toward the active area,

摘要翻译： 半导体器件包括由半导体衬底上的隔离区隔离的有源区。 晶体管包括跨越有源区延伸的栅电极，形成在栅电极两侧的有源区中的源/漏区和连接到源/漏区的含杂质的接触插塞。 源极/漏极区域通过从含杂质的接触插塞向有源区域的杂质的热扩散形成，

公开(公告)号：US20090221127A1

公开(公告)日：2009-09-03

申请号：US12464209

申请日：2009-05-12

申请人： Shinpei IIJIMA

发明人： Shinpei IIJIMA

IPC分类号： H01L21/02

CPC分类号： H01L21/02181 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3142 ,  H01L21/3162 ,  H01L21/31645 ,  H01L28/40

摘要： A stacked capacitor in a memory cell has a bottom electrode made of a metal or metal compound, a capacitor insulation film and a top electrode made of a metal or a metal compound. The capacitor insulation film includes an aluminum oxide film having a thickness of 2 to 4 nm and in contact with the bottom electrode, and an overlying hafnium oxide film having a thickness of 3 to 6 nm. The stacked capacitor has a higher resistance against a biased temperature test.

摘要翻译： 存储单元中的堆叠电容器具有由金属或金属化合物制成的底部电极，电容器绝缘膜和由金属或金属化合物制成的顶部电极。 电容绝缘膜包括厚度为2至4nm并与底部电极接触的氧化铝膜和厚度为3至6nm的上覆氧化铪膜。 堆叠式电容器对偏置温度测试具有较高的电阻。