公开(公告)号：US20120250409A1

公开(公告)日：2012-10-04

申请号：US13235430

申请日：2011-09-18

申请人： Hiroyuki KAGA ,  Masahiro Yoshihara ,  Naofumi Abiko

发明人： Hiroyuki KAGA ,  Masahiro Yoshihara ,  Naofumi Abiko

IPC分类号： G11C16/04

CPC分类号： G11C11/4096 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08

摘要： According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.

摘要翻译： 根据一个实施例，半导体存储器包括存储单元阵列，存储单元阵列包括存储单元，存储单元沿着行方向和列方向排列，并且分别存储对应于阈值的数据，控制存储器行的行控制电路 单元阵列和列控制电路，其包括控制单元，所述控制单元根据与外部地址信号对应的指针，产生对应于存储单元阵列的列的控制元件的信号。

公开(公告)号：US08472248B2

公开(公告)日：2013-06-25

申请号：US13235430

申请日：2011-09-18

申请人： Hiroyuki Kaga ,  Masahiro Yoshihara ,  Naofumi Abiko

发明人： Hiroyuki Kaga ,  Masahiro Yoshihara ,  Naofumi Abiko

IPC分类号： G11C11/34

CPC分类号： G11C11/4096 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08

摘要： According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.

摘要翻译： 根据一个实施例，半导体存储器包括存储单元阵列，存储单元阵列包括存储单元，存储单元沿着行方向和列方向排列，并且分别存储对应于阈值的数据，控制存储器行的行控制电路 单元阵列和列控制电路，其包括控制单元，所述控制单元根据与外部地址信号对应的指针，产生对应于存储单元阵列的列的控制元件的信号。

公开(公告)号：US08923074B2

公开(公告)日：2014-12-30

申请号：US13432465

申请日：2012-03-28

申请人： Masahiro Yoshihara ,  Naofumi Abiko ,  Katsumi Abe

发明人： Masahiro Yoshihara ,  Naofumi Abiko ,  Katsumi Abe

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/0483 ,  G11C16/26

摘要： A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group including one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.

摘要翻译： 感测放大器电路连接到位线，并感测并放大从存储器单元读取的信号。 第一数据锁存器通过第一总线连接到读出放大器。 第二数据锁存器连接到第二总线。 多个电路组在第一方向上重复设置，每个电路组包括一个读出放大器电路和一个第一数据锁存器。 第二数据锁存器设置在电路组和输入/输出缓冲器之间。

公开(公告)号：US07643347B2

公开(公告)日：2010-01-05

申请号：US12335093

申请日：2008-12-15

申请人： Naofumi Abiko ,  Masahiro Yoshihara

发明人： Naofumi Abiko ,  Masahiro Yoshihara

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C5/147 ,  G11C8/10 ,  G11C16/26 ,  G11C16/30

摘要： The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an operation state of each memory cell, a sense amplifier which supplies a control voltage or a control current which controls an operation state of each memory cell via the bit line according to the voltage or the current generated in the power circuit, and a transient response adjustment circuit which adjusts the transient response characteristics of the voltage or the current generated in the power supply circuit when the sense amplifier supplies to the bit line the control voltage or the control current which shifts the memory string from a first operation state to a second operation state.

摘要翻译： 与本发明的实施例相关的半导体存储器件包括连接有多个存储单元的存储器串，连接到存储器串的端部的位线，产生电压或电流相关的电源电路 提供每个存储单元的操作状态，根据在电源电路中产生的电压或电流，通过位线提供控制电压或控制电流的读出放大器，其控制每个存储单元的操作状态，以及瞬态 响应调整电路，当感测放大器向位线提供控制电压或将存储器串从第一操作状态转移到第二操作状态的控制电流时，调整在电源电路中产生的电压或电流的瞬态响应特性 操作状态

公开(公告)号：US08599613B2

公开(公告)日：2013-12-03

申请号：US13428914

申请日：2012-03-23

申请人： Naofumi Abiko ,  Masahiro Yoshihara

发明人： Naofumi Abiko ,  Masahiro Yoshihara

IPC分类号： G11C16/00

CPC分类号： G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/702

摘要： According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括存储单元阵列，其包括并行执行读和写的第一单元的存储单元，n（n是不少于2个的自然数）读出放大器，n个检测电路对应 配置成将从存储单元阵列读出的第一单位数据分割为z（z为自然数）第二单位数据的累加器，并累加第二单位数据写入不完整的故障位， 以及控制电路，被配置为控制在写入之后检测故障位的操作。

公开(公告)号：US20120250411A1

公开(公告)日：2012-10-04

申请号：US13428914

申请日：2012-03-23

申请人： Naofumi ABIKO ,  Masahiro Yoshihara

发明人： Naofumi ABIKO ,  Masahiro Yoshihara

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/702

摘要： According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括存储单元阵列，其包括并行执行读和写的第一单元的存储单元，n（n是不少于2个的自然数）读出放大器，n个检测电路对应 配置成将从存储单元阵列读出的第一单位数据分割为z（z为自然数）第二单位数据的累加器，并累加第二单位数据写入不完整的故障位， 以及控制电路，被配置为控制在写入之后检测故障位的操作。

公开(公告)号：US20090161436A1

公开(公告)日：2009-06-25

申请号：US12335093

申请日：2008-12-15

申请人： Naofumi Abiko ,  Masahiro Yoshihara

发明人： Naofumi Abiko ,  Masahiro Yoshihara

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C5/14

CPC分类号： G11C16/0483 ,  G11C5/147 ,  G11C8/10 ,  G11C16/26 ,  G11C16/30

摘要： The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an operation state of each memory cell, a sense amplifier which supplies a control voltage or a control current which controls an operation state of each memory cell via the bit line according to the voltage or the current generated in the power circuit, and a transient response adjustment circuit which adjusts the transient response characteristics of the voltage or the current generated in the power supply circuit when the sense amplifier supplies to the bit line the control voltage or the control current which shifts the memory string from a first operation state to a second operation state.

摘要翻译： 与本发明的实施例相关的半导体存储器件包括连接有多个存储单元的存储器串，连接到存储器串的端部的位线，产生电压或电流相关的电源电路 提供每个存储单元的操作状态，根据在电源电路中产生的电压或电流，通过位线提供控制电压或控制电流的读出放大器，其控制每个存储单元的操作状态，以及瞬态 响应调整电路，当感测放大器向位线提供控制电压或将存储器串从第一操作状态转移到第二操作状态的控制电流时，调整在电源电路中产生的电压或电流的瞬态响应特性 操作状态

公开(公告)号：US08274845B2

公开(公告)日：2012-09-25

申请号：US12793062

申请日：2010-06-03

申请人： Katsumi Abe ,  Masahiro Yoshihara ,  Masaru Koyanagi

发明人： Katsumi Abe ,  Masahiro Yoshihara ,  Masaru Koyanagi

IPC分类号： G11C7/00 ,  G11C16/00

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C16/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2207/2254

摘要： A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory.

摘要翻译： 提供了一种非易失性半导体存储器件，其包括：输入缓冲器，其具有能够电调节电路阈值的第一反相器;电路：具有与第一反相器相同电路结构的第二反相器的阈值监视器，用于检测电路 分别在第二反相器的输入和输出短路时第一反相器的阈值，存储与由电路阈值监视器检测的电路阈值对应的参数值的存储器，读取数据读取器电路的数据读取器电路 从存储器给予第一反相器的参数值。

公开(公告)号：US08228744B2

公开(公告)日：2012-07-24

申请号：US12693798

申请日：2010-01-26

申请人： Masahiro Yoshihara ,  Katsumi Abe

发明人： Masahiro Yoshihara ,  Katsumi Abe

IPC分类号： G11C7/10

CPC分类号： G11C7/12 ,  G11C7/08 ,  G11C2207/005

摘要： A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair.

摘要翻译： 半导体存储器件包括存储单元阵列，页缓冲器，数据线对，差分放大器和预充电器。 存储单元阵列包括多个存储单元布置在其中的多个页面。 页面缓冲器形成在与存储单元阵列相邻的位置，并且包括多个读出放大器，被配置为临时保持从页面中的存储器单元读取的页面数据。 数据线对被布置在页缓冲器中并连接到读出放大器。 差分放大器被配置为放大数据线对的线之间的电位差。 预充电器被配置为将数据线对预充电到预定电位。 差分放大器和预充电器中的至少一个形成在页面缓冲器中，并且至少一个电路电连接到数据线对。

公开(公告)号：US20110205806A1

公开(公告)日：2011-08-25

申请号：US12884721

申请日：2010-09-17

申请人： Masahiro Yoshihara ,  Teruo Takagiwa ,  Katsumi Abe

发明人： Masahiro Yoshihara ,  Teruo Takagiwa ,  Katsumi Abe

IPC分类号： G11C16/34

CPC分类号： G11C16/3436

摘要： According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元，保持电路和逻辑门极链。 存储单元与列相关联。 保持电路与列相关联，并且能够保存指示相关联的一个列是否为验证失败列的第一信息。 逻辑门链包括与列相关联并且串联连接的多个第一逻辑门。 第一逻辑门中的每一个在串联连接中将逻辑电平输出到下一级第一逻辑门。 逻辑电平基于保持电路中相关联的一个中的第一信息指示验证失败列是否存在。 使用与验证失败列相关联的第一逻辑门之一作为边界来反转从每个第一逻辑门输出的逻辑电平指示的内容。