公开(公告)号：US20100301426A1

公开(公告)日：2010-12-02

申请号：US12788784

申请日：2010-05-27

申请人： Hiroyuki KUTSUKAKE ,  Kenji GOMIKAWA ,  Yoshiko KATO ,  Mitsuhiro NOGUCHI ,  Masato ENDO

发明人： Hiroyuki KUTSUKAKE ,  Kenji GOMIKAWA ,  Yoshiko KATO ,  Mitsuhiro NOGUCHI ,  Masato ENDO

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/41775 ,  H01L29/7838

摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

摘要翻译： 半导体存储器件包括第一晶体管。 第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。 沟道区具有第一杂质浓度。 源区和漏区具有第二杂质浓度。 重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。 接触区域具有第四杂质浓度。 杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。 杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

公开(公告)号：US20100124117A1

公开(公告)日：2010-05-20

申请号：US12618200

申请日：2009-11-13

申请人： Hiroyuki KUTSUKAKE ,  Kenji GOMIKAWA ,  Mitsuhiro NOGUCHI ,  Kikuko SUGIMAE ,  Masato Endo ,  Takuya FUTATSUYAMA ,  Koji KATO ,  Kanae UCHIDA

发明人： Hiroyuki KUTSUKAKE ,  Kenji GOMIKAWA ,  Mitsuhiro NOGUCHI ,  Kikuko SUGIMAE ,  Masato Endo ,  Takuya FUTATSUYAMA ,  Koji KATO ,  Kanae UCHIDA

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/16 ,  H01L27/11521 ,  H01L27/11526

摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.

摘要翻译： 存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线 第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。 控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向 第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。

公开(公告)号：US20110220996A1

公开(公告)日：2011-09-15

申请号：US12885031

申请日：2010-09-17

申请人： Hiroyuki KUTSUKAKE ,  Kenji Gomikawa ,  Yoshiko Kato ,  Norihisa Arai ,  Tomoaki Hatano

发明人： Hiroyuki KUTSUKAKE ,  Kenji Gomikawa ,  Yoshiko Kato ,  Norihisa Arai ,  Tomoaki Hatano

IPC分类号： H01L27/088 ,  H01L21/762

CPC分类号： H01L27/11519 ,  H01L21/76229 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, an element isolation insulating film, a source layer, a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The semiconductor substrate is a first conductivity type. The element isolation insulating film divides an upper layer portion of the semiconductor substrate into a plurality of first active regions. The source layer and the drain layer are a second conductivity type and are formed in spaced to each other in an upper portion of each of the first active regions. The gate electrode is provided in a region directly above a channel region on the semiconductor substrate located between the source layer and the drain layer. The gate insulating film is provided between the semiconductor substrate and the gate electrode. The first punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region.

摘要翻译： 根据一个实施例，半导体器件包括半导体衬底，元件隔离绝缘膜，源极层，漏极层，栅电极，栅极绝缘膜，第一穿通阻挡层和第二穿通 塞层。 半导体衬底是第一导电类型。 元件隔离绝缘膜将半导体衬底的上层部分分成多个第一有源区。 源层和漏极层是第二导电类型，并且在每个第一有源区的上部彼此间隔开形成。 栅电极设置在位于源层和漏极层之间的半导体衬底上的沟道区的正上方的区域中。 栅极绝缘膜设置在半导体衬底和栅电极之间。 第一导电类型的第一穿通阻挡层形成在源极的正下方的第一有源区的区域中，并且第一导电类型的第二穿通阻挡层形成在第一有源区的区域中 直接在漏极层下面。 第一穿通阻止层和第二穿通阻止层各自具有高于半导体衬底的有效杂质浓度。 第一穿通阻止层和源极层在沟道区域中分离。 第二穿通阻止层和漏极层在沟道区域中分离。

公开(公告)号：US20100270606A1

公开(公告)日：2010-10-28

申请号：US12765477

申请日：2010-04-22

申请人： Hiroyuki KUTSUKAKE ,  Takayuki TOBA ,  Yoshiko KATO ,  Kenji GOMIKAWA ,  Haruhiko KOYAMA

发明人： Hiroyuki KUTSUKAKE ,  Takayuki TOBA ,  Yoshiko KATO ,  Kenji GOMIKAWA ,  Haruhiko KOYAMA

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

摘要翻译： 在存储单元阵列区域周围形成外围电路区域。 外围电路区域具有元件区域，隔离元件区域的元件隔离区域和形成在每个元件区域中并包括在沟道宽度方向上延伸的栅电极的场效应晶体管。 栅电极的端部和角部位于元件隔离区上。 栅电极的角部的曲率半径比从沟道宽度方向的元件区域的端部到沟道宽度方向的栅电极的端部的长度小，并且小于85nm 。

公开(公告)号：US20120032243A1

公开(公告)日：2012-02-09

申请号：US13052152

申请日：2011-03-21

申请人： Hiroyuki KUTSUKAKE ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

发明人： Hiroyuki KUTSUKAKE ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

IPC分类号： H01L29/94

CPC分类号： H01L27/11526 ,  H01L27/11521 ,  H01L27/11529

摘要： According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

摘要翻译： 根据一个实施例，半导体器件包括设置在半导体衬底中的至少一个半导体区域和包括设置在半导体区域中的多个电容器的电容器组，每个电容器包括设置在半导体区域上的电容器绝缘膜，电容器 设置在电容器绝缘膜上的电极以及设置在与电容器电极相邻的半导体区域中的至少一个扩散层。

公开(公告)号：US20120236619A1

公开(公告)日：2012-09-20

申请号：US13231510

申请日：2011-09-13

申请人： Hiroyuki KUTSUKAKE ,  Kikuko SUGIMAE ,  Mitsuhiro NOGUCHI

发明人： Hiroyuki KUTSUKAKE ,  Kikuko SUGIMAE ,  Mitsuhiro NOGUCHI

IPC分类号： G11C5/06

CPC分类号： G11C16/0483 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11519 ,  H01L27/11529

摘要： According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器阵列和外围电路。 存储器阵列具有多个存储单元，字线和位线，其中按照位线的顺序设置第一，第二和第三块。 外围电路具有晶体管组。 晶体管组包括属于第一块的第一转移晶体管，属于第二块的第二转移晶体管和属于第三块的第三转移晶体管。 第一，第二和第三转移晶体管共享每个的源极和漏极中的另一个。 关于源极和漏极中的任一个与第一，第二和第三转移晶体管中的每一个连接到另一个的方向，相邻的转移晶体管的方向彼此相差90°或180° 。

公开(公告)号：US20130069133A1

公开(公告)日：2013-03-21

申请号：US13415010

申请日：2012-03-08

申请人： Yoshiko KATO ,  Hiroyuki KUTSUKAKE

发明人： Yoshiko KATO ,  Hiroyuki KUTSUKAKE

IPC分类号： H01L29/78

CPC分类号： H01L27/11558 ,  H01L27/11531

摘要： A semiconductor device, includes: a semiconductor substrate; a first conductivity type well and a second conductivity type well; a first active area; a second active area; a first well contact layer; a plurality of first source/drain layers; a first gate insulating film; a first gate electrode; a second well contact layer; a plurality of second source/drain layers; a second gate insulating film; and a second gate electrode. The first well contact layer is formed in the first active area at one end part in the one direction. The one end parts in each of the first active areas and in each of the second active areas are mutually on the same side.

摘要翻译： 一种半导体器件，包括：半导体衬底; 第一导电类型井和第二导电类型井; 第一个活跃区域; 第二个活跃区域; 第一阱接触层; 多个第一源极/漏极层; 第一栅极绝缘膜; 第一栅电极; 第二阱接触层; 多个第二源极/漏极层; 第二栅绝缘膜; 和第二栅电极。 第一阱接触层在一个方向上的一个端部的第一有源区域中形成。 第一有效区域和第二有源区域中的每一个中的一端部分彼此相同。

公开(公告)号：US20120217584A1

公开(公告)日：2012-08-30

申请号：US13226763

申请日：2011-09-07

申请人： Hiroyuki KUTSUKAKE ,  Yoshiko Kato

发明人： Hiroyuki KUTSUKAKE ,  Yoshiko Kato

IPC分类号： H01L27/088

CPC分类号： H01L27/11524 ,  H01L27/11519 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a semiconductor memory device includes a substrate, and device regions in the substrate to extend in a first direction. The device further includes select gates on the substrate to extend in a second direction, and a contact region provided between the select gates and including contact plugs on the respective device regions. The contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. The contact region includes the partial regions of at least two types whose values of N are different. Further, each of the contact plugs has a planar shape of an ellipse, and is arranged so that a major axis of the ellipse is tilted with respect to the first direction.

摘要翻译： 在一个实施例中，半导体存储器件包括衬底以及衬底中沿第一方向延伸的器件区域。 该装置还包括在基板上沿第二方向延伸的选择栅极以及设置在选择栅极之间并包括各个器件区域上的接触插塞的接触区域。 接触区域包括部分区域，其中每个N个接触插塞设置在N个连续的器件区域上，以布置在不平行于第一和第二方向的直线上，其中N是2或更大的整数。 接触区域包括N值不同的至少两种类型的部分区域。 此外，每个接触插塞具有椭圆形的平面形状，并且被布置成使得椭圆的长轴相对于第一方向倾斜。

公开(公告)号：US20100013028A1

公开(公告)日：2010-01-21

申请号：US12501726

申请日：2009-07-13

申请人： Yoshiko KATO ,  Hiroyuki KUTSUKAKE

发明人： Yoshiko KATO ,  Hiroyuki KUTSUKAKE

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/823481 ,  H01L21/823462 ,  H01L27/088

摘要： A semiconductor device with a high-voltage transistor and a low-voltage transistor includes an isolation insulating film between a first element region of the high-voltage transistor and a second element region of the low-voltage transistor, a first gate insulating film on a semiconductor substrate in the first element region, a first gate electrode on the first gate insulating film, a second gate insulating film on the semiconductor substrate in the second element region, and a second gate electrode on the second gate insulating film. The isolation insulating film includes a first isolation region adjacent to a surrounding area of the first element region and a second isolation region adjacent to a surrounding area of the second element region. A bottom of the second isolation region is lower than a bottom of the first isolation region. The first gate insulating film is thicker than the second gate insulating film.

摘要翻译： 具有高压晶体管和低压晶体管的半导体器件包括在高压晶体管的第一元件区域和低压晶体管的第二元件区域之间的隔离绝缘膜，第一栅极绝缘膜 第一元件区域中的半导体衬底，第一栅极绝缘膜上的第一栅极电极，第二元件区域中的半导体衬底上的第二栅极绝缘膜，以及第二栅极绝缘膜上的第二栅极电极。 隔离绝缘膜包括与第一元件区域的周围区域相邻的第一隔离区域和与第二元件区域的周围区域相邻的第二隔离区域。 第二隔离区域的底部低于第一隔离区域的底部。 第一栅极绝缘膜比第二栅极绝缘膜厚。

公开(公告)号：US20120235218A1

公开(公告)日：2012-09-20

申请号：US13235397

申请日：2011-09-18

申请人： Hiroyuki KUTSUKAKE ,  Noboru Shibata ,  Kazushige Kanda ,  Masayuki Ichige

发明人： Hiroyuki KUTSUKAKE ,  Noboru Shibata ,  Kazushige Kanda ,  Masayuki Ichige

IPC分类号： H01L27/115 ,  H01L21/8239

CPC分类号： H01L27/11529 ,  G11C11/5621 ,  G11C16/0483 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/11546

摘要： According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well.

摘要翻译： 根据一个实施例，一种器件包括半导体衬底，第一区域，包括形成在衬底中的第一阱，形成在衬底中的第二阱和第一阱，以及形成在第二阱上的存储单元，以及 包括形成在衬底中的第三阱的第二区域和形成在第三阱上的第一晶体管。 该器件包括第三区域，该第三区域包括形成在半导体衬底上的第二晶体管，以及第四区域，包括形成在半导体衬底中的第四阱，形成在衬底中的第五阱和第四阱，以及第三晶体管， 形成在第五井。 第一井和第四井的底部低于第三井的底部，第三井的底部低于第二井和第五井的底部。