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    WIRELESS BASE STATION AND WIRELESS COMMUNICATION SYSTEM USING THE SAME
    1.
    发明申请
    WIRELESS BASE STATION AND WIRELESS COMMUNICATION SYSTEM USING THE SAME 有权
    无线基站和无线通信系统

    公开(公告)号：US20130336188A1

    公开(公告)日：2013-12-19

    申请号：US14000773

    申请日：2012-02-16

    申请人： Hiroyuki Yomo ,  Yoshihisa Kondo ,  Suhua Tang ,  Sadao Obana ,  Tetsuya Ito ,  Akira Matsumoto ,  Koichi Yoshimura

    发明人： Hiroyuki Yomo ,  Yoshihisa Kondo ,  Suhua Tang ,  Sadao Obana ,  Tetsuya Ito ,  Akira Matsumoto ,  Koichi Yoshimura

    IPC分类号： H04W52/02

    CPC分类号： H04W52/0206 ,  Y02B70/32 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/162

    摘要： A wireless base station (1) includes a wakeup device (13) and a main device (14). When the main device (14) is in a sleep mode, the wakeup device (13) is connected to the antenna (11). Then, when the wakeup device (13) receives a wakeup signal for activating the wireless base station (1) from a terminal device assigned to the wireless base station (1) in a communication band used for wireless communication with the terminal device and when the information for identifying a wireless base station to be activated contained in the received wakeup signal is identical with the identification information of the wireless base station (1), the wakeup device (13) outputs a driving signal to the main device (14). The main device (14) transitions from the sleep mode to an operating mode in response to the driving signal from the wakeup device (13).

    摘要翻译： 无线基站（1）包括唤醒设备（13）和主设备（14）。 当主设备（14）处于睡眠模式时，唤醒设备（13）连接到天线（11）。 然后，当唤醒装置（13）在与终端装置进行无线通信的通信频带中从分配给无线基站（1）的终端装置接收到激活无线基站（1）的唤醒信号时， 用于识别接收到的唤醒信号中包含的要激活的无线基站的信息与无线基站（1）的识别信息相同，所述唤醒设备（13）向主设备（14）输出驱动信号。 响应于来自唤醒装置（13）的驱动信号，主装置（14）从睡眠模式转换到操作模式。

    Wireless base station and wireless communication system using the same
    2.
    发明授权
    Wireless base station and wireless communication system using the same 有权
    无线基站和无线通信系统使用相同

    公开(公告)号：US09521613B2

    公开(公告)日：2016-12-13

    申请号：US14000773

    申请日：2012-02-16

    申请人： Hiroyuki Yomo ,  Yoshihisa Kondo ,  Suhua Tang ,  Sadao Obana ,  Tetsuya Ito ,  Akira Matsumoto ,  Koichi Yoshimura

    发明人： Hiroyuki Yomo ,  Yoshihisa Kondo ,  Suhua Tang ,  Sadao Obana ,  Tetsuya Ito ,  Akira Matsumoto ,  Koichi Yoshimura

    IPC分类号： H04W52/02

    CPC分类号： H04W52/0206 ,  Y02B70/32 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/162

    摘要： A wireless base station (1) includes a wakeup device (13) and a main device (14). When the main device (14) is in a sleep mode, the wakeup device (13) is connected to the antenna (11). Then, when the wakeup device (13) receives a wakeup signal for activating the wireless base station (1) from a terminal device assigned to the wireless base station (1) in a communication band used for wireless communication with the terminal device and when the information for identifying a wireless base station to be activated contained in the received wakeup signal is identical with the identification information of the wireless base station (1), the wakeup device (13) outputs a driving signal to the main device (14). The main device (14) transitions from the sleep mode to an operating mode in response to the driving signal from the wakeup device (13).

    摘要翻译： 无线基站（1）包括唤醒设备（13）和主设备（14）。 当主设备（14）处于睡眠模式时，唤醒设备（13）连接到天线（11）。 然后，当唤醒装置（13）在与终端装置进行无线通信的通信频带中从分配给无线基站（1）的终端装置接收到激活无线基站（1）的唤醒信号时， 用于识别接收到的唤醒信号中包含的要激活的无线基站的信息与无线基站（1）的识别信息相同，所述唤醒设备（13）向主设备（14）输出驱动信号。 响应于来自唤醒装置（13）的驱动信号，主装置（14）从睡眠模式转换到操作模式。

    Non-volatile semiconductor storage device
    8.
    发明授权
    Non-volatile semiconductor storage device 有权
    非易失性半导体存储装置

    公开(公告)号：US08279670B2

    公开(公告)日：2012-10-02

    申请号：US12882507

    申请日：2010-09-15

    申请人： Takuya Futatsuyama ,  Yoshihisa Kondo ,  Noboru Shibata

    发明人： Takuya Futatsuyama ,  Yoshihisa Kondo ,  Noboru Shibata

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C8/00 ,  G11C11/5621 ,  G11C16/0483 ,  G11C2211/5641

    摘要： A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.

    摘要翻译： 根据实施例的非易失性半导体存储装置包括：包括电可重写存储器单元阵列的存储单元阵列，并且被配置为能够将N位数据（其中N是不小于2的自然数）存储在一个 记忆体; 以及控制器，用于控制存储单元阵列的读，写和擦除操作。 存储单元阵列包括具有第一存储器单元的第一区域，该第一存储器单元可操作以保留N位数据，以及具有第二存储单元的第二区域，该第二存储单元可操作以保持M位数据（其中M是小于N的自然数）。 当访问第一存储器单元时，由控制器接收的地址数据的数据结构与在访问第二存储单元时从外部接收的地址数据的数据结构相同。

    Non-volatile semiconductor memory device and electric device with the same
    10.
    发明申请
    Non-volatile semiconductor memory device and electric device with the same 有权

    公开(公告)号：US20050135183A1

    公开(公告)日：2005-06-23

    申请号：US10829267

    申请日：2004-04-22

    申请人： Yoshihisa Kondo

    发明人： Yoshihisa Kondo

    IPC分类号： G11C16/02 ,  G11C8/00 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/32

    CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/32

    摘要： A non-volatile semiconductor memory device has a memory core circuit including a cell array in which electrically rewritable and non-volatile memory cells are arranged therein, decoders configured to select the memory cells, and sense amplifiers configured to perform data read and write of the cell array, and a peripheral circuit including a memory controller configured to control data read and write in communication with the memory core circuit, wherein the memory controller has: an oscillator configured to generate an internal clock signal; a timing control circuit configured to timing control timings of data read and write of the cell array as synchronous with the internal clock signal; and a merge clock generation circuit configured to generate based on an external timing signal and the internal clock signal a merge clock signal serving for timing controlling a circuit portion in the peripheral circuit, the merge clock signal being defined as having a first signal period in which the external timing signal serves as a clock source and a second signal period without overlapping the first signal period, in which the internal clock signal serves as a clock source.