公开(公告)号：US07450461B2

公开(公告)日：2008-11-11

申请号：US11543227

申请日：2006-10-05

申请人： Hisakazu Kotani ,  Motonobu Nishimura ,  Kazuyo Nishikawa ,  Masahiro Ueminami

发明人： Hisakazu Kotani ,  Motonobu Nishimura ,  Kazuyo Nishikawa ,  Masahiro Ueminami

IPC分类号： G11C8/00

CPC分类号： G11C7/1042 ,  G11C8/12 ,  G11C11/005

摘要： In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

摘要翻译： 在使用具有多个CPU的多个存储器的系统中，将多个存储器阵列放置在相同的存储器芯片上，每个存储器阵列分别设置有数据相关电路，地址相关电路和控制 - 相关电路。 然而，这些存储器阵列共享数据终端，地址终端和用于芯片外部连接的控制终端。 通过经阵列选择信号（时钟）控制的三个信号选择电路的MUX将数据，地址和控制信号分配到存储器阵列。 在时钟的上升时刻，信号被提供给一个存储器阵列，同时在时钟的下降定时将信号提供给另一个存储器阵列。 因此，在将多个存储器阵列放置在一个芯片上的存储器集成中，可获得每个存储器阵列的独立操作，并且不需要CPU之间的总线仲裁。

公开(公告)号：US20070081398A1

公开(公告)日：2007-04-12

申请号：US11543227

申请日：2006-10-05

申请人： Hisakazu Kotani ,  Motonobu Nishimura ,  Kazuyo Nishikawa ,  Masahiro Ueminami

发明人： Hisakazu Kotani ,  Motonobu Nishimura ,  Kazuyo Nishikawa ,  Masahiro Ueminami

IPC分类号： G11C7/10

CPC分类号： G11C7/1042 ,  G11C8/12 ,  G11C11/005

摘要： In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

摘要翻译： 在使用具有多个CPU的多个存储器的系统中，将多个存储器阵列放置在相同的存储器芯片上，每个存储器阵列分别设置有数据相关电路，地址相关电路和控制 - 相关电路。 然而，这些存储器阵列共享数据终端，地址终端和用于芯片外部连接的控制终端。 通过经阵列选择信号（时钟）控制的三个信号选择电路的MUX将数据，地址和控制信号分配到存储器阵列。 在时钟的上升时刻，信号被提供给一个存储器阵列，同时在时钟的下降定时将信号提供给另一个存储器阵列。 因此，在将多个存储器阵列放置在一个芯片上的存储器集成中，可获得每个存储器阵列的独立操作，并且不需要CPU之间的总线仲裁。

公开(公告)号：US20080028132A1

公开(公告)日：2008-01-31

申请号：US11798679

申请日：2007-05-16

申请人： Masanori Matsuura ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yoshiaki Nakao ,  Hisakazu Kotani ,  Junichi Kato ,  Satoshi Mishima ,  Motonobu Nishimura ,  Toshiki Mori

发明人： Masanori Matsuura ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yoshiaki Nakao ,  Hisakazu Kotani ,  Junichi Kato ,  Satoshi Mishima ,  Motonobu Nishimura ,  Toshiki Mori

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F13/1668 ,  G06F2212/7203 ,  G11C16/10

摘要： A non-volatile storage device comprises a non-volatile memory into which data is written per unit area, and a memory controller for controlling writing of data into the non-volatile memory. The memory controller comprises a first storage section for holding data input from the outside of the device, a first control section for writing data which is held by the first storage section and whose amount corresponds to the unit area, into the non-volatile memory in a unit area-by-unit area basis, and writing data which is held by the first storage section and whose amount is less than the unit area, into a second storage section, and a second control section for writing data held by the second storage section into the non-volatile memory.

摘要翻译： 非易失性存储装置包括：每单位区域写入数据的非易失性存储器;以及用于控制将数据写入非易失性存储器的存储器控​​制器。 存储器控制器包括用于保存从设备外部输入的数据的第一存储部分，用于将由第一存储部分保存并且其数量对应于单位区域的数据写入到非易失性存储器中的第一控制部分 以单位面积为单位的区域，以及将由第一存储部保持的数量小于单位面积的写入数据写入到第二存储部中，以及第二控制部，用于写入由第二存储器 部分进入非易失性存储器。

公开(公告)号：US07105929B2

公开(公告)日：2006-09-12

申请号：US10791805

申请日：2004-03-04

申请人： Katsuhiko Shishido ,  Motonobu Nishimura ,  Hisakazu Kotani

发明人： Katsuhiko Shishido ,  Motonobu Nishimura ,  Hisakazu Kotani

IPC分类号： H01L23/48

CPC分类号： H01L23/49503 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A first semiconductor chip 102 includes an integrated circuit formed on a face which is shown upwards in FIG. 2. A second semiconductor chip 103 includes an integrated circuit formed on a face which is shown downwards in FIG. 2. Between the first semiconductor chip 102 and the second semiconductor chip 103, a non-conductive die pad 107 is interposed. The die pad 107 is provided with connection members 110 protruding from the first semiconductor chip 102 and the second semiconductor chip 103. The connection members 110 are plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chip 102 and the integrated circuit on the second semiconductor chip 103 are interconnected by two inter-chip connection wires 104a and 104b, via the connection members 110. Thus, there is provided a semiconductor device composed of a plurality of internally connected semiconductor chips, such that the semiconductor device is easy to produce and requires a reduced number of component elements.

摘要翻译： 第一半导体芯片102包括形成在图1中向上示出的面上的集成电路。 2。 第二半导体芯片103包括形成在图1中向下示出的面上的集成电路。 2。 在第一半导体芯片102和第二半导体芯片103之间插入非导电芯片焊盘107。 管芯焊盘107设置有从第一半导体芯片102和第二半导体芯片103突出的连接构件110。 连接构件110在其表面上电镀以导电。 第一半导体芯片102上的集成电路和第二半导体芯片103上的集成电路经由连接构件110通过两个芯片间连接线104a和104b互连。 因此，提供了由多个内部连接的半导体芯片组成的半导体器件，使得半导体器件易于制造并且需要数量少的元件元件。

公开(公告)号：US07251717B2

公开(公告)日：2007-07-31

申请号：US10863328

申请日：2004-06-09

申请人： Kazuyo Nishikawa ,  Motonobu Nishimura

发明人： Kazuyo Nishikawa ,  Motonobu Nishimura

IPC分类号： G06F12/00

CPC分类号： G11C16/105 ,  G06F12/0246 ,  G11C16/102

摘要： While a plurality of physical address memories are provided with respect to one logical address of a non-volatile memory device, an empty physical address memory contained in the plural physical address memories is searched with respect to a writing operation for one logical address, and then, data is written in this empty physical address memory. With respect to a reading operation for one logical address, such a physical address memory to which data has been written at last is searched, and the storage content of this memory is read out. As a result, the data rewriting operation to a non-volatile memory can be carried out with employment of the simple circuit arrangement with respect to one logical address, while an erasing operation is not performed, and an area of a memory device is not increased but also a total number of data rewriting operation is not limited to a number defined in a specification of the memory device.

摘要翻译： 虽然相对于非易失性存储器件的一个逻辑地址提供了多个物理地址存储器，但是对于一个逻辑地址的写操作搜索包含在多个物理地址存储器中的空物理地址存储器，然后 数据写在这个空的物理地址存储器中。 对于一个逻辑地址的读取操作，搜索最后写入数据的物理地址存储器，并读出该存储器的存储内容。 结果，可以通过使用关于一个逻辑地址的简单电路布置来执行对非易失性存储器的数据重写操作，而不执行擦除操作，并且存储器件的区域不增加 而且数据重写操作的总数不限于在存储器件的规格中定义的数量。