公开(公告)号：US07450461B2

公开(公告)日：2008-11-11

申请号：US11543227

申请日：2006-10-05

申请人： Hisakazu Kotani ,  Motonobu Nishimura ,  Kazuyo Nishikawa ,  Masahiro Ueminami

发明人： Hisakazu Kotani ,  Motonobu Nishimura ,  Kazuyo Nishikawa ,  Masahiro Ueminami

IPC分类号： G11C8/00

CPC分类号： G11C7/1042 ,  G11C8/12 ,  G11C11/005

摘要： In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

摘要翻译： 在使用具有多个CPU的多个存储器的系统中，将多个存储器阵列放置在相同的存储器芯片上，每个存储器阵列分别设置有数据相关电路，地址相关电路和控制 - 相关电路。 然而，这些存储器阵列共享数据终端，地址终端和用于芯片外部连接的控制终端。 通过经阵列选择信号（时钟）控制的三个信号选择电路的MUX将数据，地址和控制信号分配到存储器阵列。 在时钟的上升时刻，信号被提供给一个存储器阵列，同时在时钟的下降定时将信号提供给另一个存储器阵列。 因此，在将多个存储器阵列放置在一个芯片上的存储器集成中，可获得每个存储器阵列的独立操作，并且不需要CPU之间的总线仲裁。

公开(公告)号：US20070081398A1

公开(公告)日：2007-04-12

申请号：US11543227

申请日：2006-10-05

申请人： Hisakazu Kotani ,  Motonobu Nishimura ,  Kazuyo Nishikawa ,  Masahiro Ueminami

发明人： Hisakazu Kotani ,  Motonobu Nishimura ,  Kazuyo Nishikawa ,  Masahiro Ueminami

IPC分类号： G11C7/10

CPC分类号： G11C7/1042 ,  G11C8/12 ,  G11C11/005

摘要： In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

摘要翻译： 在使用具有多个CPU的多个存储器的系统中，将多个存储器阵列放置在相同的存储器芯片上，每个存储器阵列分别设置有数据相关电路，地址相关电路和控制 - 相关电路。 然而，这些存储器阵列共享数据终端，地址终端和用于芯片外部连接的控制终端。 通过经阵列选择信号（时钟）控制的三个信号选择电路的MUX将数据，地址和控制信号分配到存储器阵列。 在时钟的上升时刻，信号被提供给一个存储器阵列，同时在时钟的下降定时将信号提供给另一个存储器阵列。 因此，在将多个存储器阵列放置在一个芯片上的存储器集成中，可获得每个存储器阵列的独立操作，并且不需要CPU之间的总线仲裁。

公开(公告)号：US07030639B2

公开(公告)日：2006-04-18

申请号：US10776237

申请日：2004-02-12

申请人： Masahiro Ueminami ,  Hisakazu Kotani ,  Katsuhiko Shishido

发明人： Masahiro Ueminami ,  Hisakazu Kotani ,  Katsuhiko Shishido

IPC分类号： G01R31/26

CPC分类号： G01R31/2853 ,  H01L22/34 ,  H01L2224/05554 ,  H01L2224/48145 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor apparatus includes serially-connected bodies composed of a switch element and a resistance element respectively interposed between terminals adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected bodies, and a switch control terminal for collectively controlling all the plural switch elements. Also included are switch elements interposed alternately on the first semiconductor chip side and the second semiconductor chip side between wires adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected switch elements, and a switch control terminal for collectively controlling all the plural switch elements.

摘要翻译： 一种半导体装置，包括：串联连接体，分别插在彼此相邻的端子之间的开关元件和电阻元件;连接到一系列串联体的一端和另一端的导通测试端子，以及开关控制 用于集体控制所有多个开关元件的端子。 还包括在第一半导体芯片侧交替设置的开关元件和彼此相邻的布线之间的第二半导体芯片侧，连接到一系列串联连接的开关元件的一端和另一端的导通测试端子，以及开关 用于集体控制所有多个开关元件的控制端子。

公开(公告)号：US20080028132A1

公开(公告)日：2008-01-31

申请号：US11798679

申请日：2007-05-16

申请人： Masanori Matsuura ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yoshiaki Nakao ,  Hisakazu Kotani ,  Junichi Kato ,  Satoshi Mishima ,  Motonobu Nishimura ,  Toshiki Mori

发明人： Masanori Matsuura ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yoshiaki Nakao ,  Hisakazu Kotani ,  Junichi Kato ,  Satoshi Mishima ,  Motonobu Nishimura ,  Toshiki Mori

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F13/1668 ,  G06F2212/7203 ,  G11C16/10

摘要： A non-volatile storage device comprises a non-volatile memory into which data is written per unit area, and a memory controller for controlling writing of data into the non-volatile memory. The memory controller comprises a first storage section for holding data input from the outside of the device, a first control section for writing data which is held by the first storage section and whose amount corresponds to the unit area, into the non-volatile memory in a unit area-by-unit area basis, and writing data which is held by the first storage section and whose amount is less than the unit area, into a second storage section, and a second control section for writing data held by the second storage section into the non-volatile memory.

摘要翻译： 非易失性存储装置包括：每单位区域写入数据的非易失性存储器;以及用于控制将数据写入非易失性存储器的存储器控​​制器。 存储器控制器包括用于保存从设备外部输入的数据的第一存储部分，用于将由第一存储部分保存并且其数量对应于单位区域的数据写入到非易失性存储器中的第一控制部分 以单位面积为单位的区域，以及将由第一存储部保持的数量小于单位面积的写入数据写入到第二存储部中，以及第二控制部，用于写入由第二存储器 部分进入非易失性存储器。

公开(公告)号：US07105929B2

公开(公告)日：2006-09-12

申请号：US10791805

申请日：2004-03-04

申请人： Katsuhiko Shishido ,  Motonobu Nishimura ,  Hisakazu Kotani

发明人： Katsuhiko Shishido ,  Motonobu Nishimura ,  Hisakazu Kotani

IPC分类号： H01L23/48

CPC分类号： H01L23/49503 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A first semiconductor chip 102 includes an integrated circuit formed on a face which is shown upwards in FIG. 2. A second semiconductor chip 103 includes an integrated circuit formed on a face which is shown downwards in FIG. 2. Between the first semiconductor chip 102 and the second semiconductor chip 103, a non-conductive die pad 107 is interposed. The die pad 107 is provided with connection members 110 protruding from the first semiconductor chip 102 and the second semiconductor chip 103. The connection members 110 are plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chip 102 and the integrated circuit on the second semiconductor chip 103 are interconnected by two inter-chip connection wires 104a and 104b, via the connection members 110. Thus, there is provided a semiconductor device composed of a plurality of internally connected semiconductor chips, such that the semiconductor device is easy to produce and requires a reduced number of component elements.

摘要翻译： 第一半导体芯片102包括形成在图1中向上示出的面上的集成电路。 2。 第二半导体芯片103包括形成在图1中向下示出的面上的集成电路。 2。 在第一半导体芯片102和第二半导体芯片103之间插入非导电芯片焊盘107。 管芯焊盘107设置有从第一半导体芯片102和第二半导体芯片103突出的连接构件110。 连接构件110在其表面上电镀以导电。 第一半导体芯片102上的集成电路和第二半导体芯片103上的集成电路经由连接构件110通过两个芯片间连接线104a和104b互连。 因此，提供了由多个内部连接的半导体芯片组成的半导体器件，使得半导体器件易于制造并且需要数量少的元件元件。

公开(公告)号：US07991945B2

公开(公告)日：2011-08-02

申请号：US12136340

申请日：2008-06-10

申请人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

发明人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

IPC分类号： G06F13/00 ,  G06F13/28 ,  G11C7/00

CPC分类号： G11C16/26 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1063

摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

摘要翻译： 一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作 块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

公开(公告)号：US5740114A

公开(公告)日：1998-04-14

申请号：US438919

申请日：1995-05-10

申请人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

发明人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

IPC分类号： G11C29/00 ,  G11C29/24 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/24 ,  G11C29/812 ,  G11C29/844

摘要： An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

公开(公告)号：US5699300A

公开(公告)日：1997-12-16

申请号：US341947

申请日：1994-11-16

申请人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

发明人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C11/409 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1015 ,  G11C8/14 ,  G11C8/18

摘要： A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.

摘要翻译： 一种半导体存储器件，包括以矩阵形式布置的存储器单元，其中多对位线被列地址并连接到读出放大器，并且字线被行寻址并分成划分字线。 由列寻址选择的读出放大器的输出信号被传送到相应的数据线。 分割字线对应于行寻址而被时间顺序地激活，其中任何两个连续分割字线的激活状态在完全激活时间的分数时间内重叠。 感测放大器被分组成具有相应公共列地址的多个组。 每组读出放大器的输出都被施加到连接到串行/并行转换器的相应数据线上。

公开(公告)号：US20050077600A1

公开(公告)日：2005-04-14

申请号：US10952796

申请日：2004-09-30

申请人： Hisakazu Kotani

发明人： Hisakazu Kotani

IPC分类号： H01L25/18 ,  G11C5/06 ,  G11C29/02 ,  H01L23/52 ,  H01L25/04 ,  H01L23/58 ,  H01L23/495 ,  H01L29/10

CPC分类号： H01L25/18 ,  G11C5/06 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C2029/5006 ,  H01L25/065 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The SIP structure package includes a first chip though which signal transmission/reception is performed between the inside and the outside of the package, and a second chip connected to the first chip within the package. The first chip includes interface circuits 6A and 6B for supplying a signal to all the signal terminals of the second chip. The operation of the interface circuits is controlled to be stoppable by a control signal.

摘要翻译： SIP结构封装包括第一芯片，其中在封装的内部和外部之间执行信号发送/接收，以及连接到封装内的第一芯片的第二芯片。 第一芯片包括用于向第二芯片的所有信号端子提供信号的接口电路6A和6B。 通过控制信号控制接口电路的动作。

公开(公告)号：US5764566A

公开(公告)日：1998-06-09

申请号：US893682

申请日：1997-07-11

申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

CPC分类号： G11C11/412 ,  G11C11/417

摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。