公开(公告)号：US11507307B2

公开(公告)日：2022-11-22

申请号：US16801334

申请日：2020-02-26

Applicant: Hitachi, Ltd.

Inventor： Kentaro Shimada ,  Akira Yamamoto ,  Katsuya Tanaka

IPC: G06F3/06

Abstract: A storage system includes a plurality of storage controllers and a drive box including one or more non-volatile storage devices. The drive box includes a memory on which reading and writing are performed in a unit different from a unit for reading and writing the one or more non-volatile storage devices, and which stores control information to be used by the plurality of storage controllers, and a memory controller that enables each storage controller of the plurality of storage controllers to exclusively read and write the control information of the memory by arbitrating accesses to the memory from the plurality of storage controllers.

公开(公告)号：US10970237B2

公开(公告)日：2021-04-06

申请号：US16561154

申请日：2019-09-05

Applicant: Hitachi, Ltd.

Inventor： Katsuya Tanaka ,  Kentaro Shimada

IPC: G06F13/16 ,  G06F12/0806 ,  G06F13/28 ,  G06F13/42 ,  G06F13/40

Abstract: A first storage controller includes a first processor, a first memory, and a first switch having a first port. A second storage controller includes a second processor, a second memory, and a second switch having a second port. A storage system connects the first port and the second port by a first link. The first processor and the first switch are connected by a second link configured to transfer user data and a third link configured to transfer control data. The second processor and the second switch are connected by a fourth link configured to transfer user data and a fifth link configured to transfer control data. The first port and the second port transfer the control data in preference to the user data on the first link.

公开(公告)号：US12197325B2

公开(公告)日：2025-01-14

申请号：US18368502

申请日：2023-09-14

Applicant: Hitachi, Ltd.

Inventor： Katsuya Tanaka ,  Kentaro Shimada

IPC: G06F12/02 ,  G06F13/16 ,  G06F13/18 ,  G06F13/40

Abstract: A frontend interface of a controller according to the present invention includes a plurality of corresponding queueing interfaces for each processor of the controller, and an enqueueing destination of a host I/O command can be switched in response to an instruction from a processor. When a controller OS restarts, the controller waits for completion of a host I/O and executes controller blocking and restarting during setup. Therefore, to determine whether or not this process is possible, the processor gives an instruction to switch a queue and waits until a switch source queue is empty.

公开(公告)号：US11347672B2

公开(公告)日：2022-05-31

申请号：US17010691

申请日：2020-09-02

Applicant: Hitachi, Ltd.

Inventor： Katsuya Tanaka ,  Hirotoshi Akaike

IPC: G06F13/40 ,  G06F15/173

Abstract: A storage apparatus in which a controller reads out a port status of a switch in a short period of time is disclosed. The storage apparatus includes a switch and a plurality of storage controllers configured to communicate with each other through the switch. The switch includes a switch processor, a plurality of data ports, a switch integrated circuit, a memory, and a management interface. One of the plurality of data ports and a management port of the management interface are connected to each other. The switch processor stores a status of the plurality of data ports acquired from the switch integrated circuit into the memory. The plurality of storage controllers access the management interface through the plurality of data ports and the management port and receive the statuses of the plurality of data ports stored in the memory from the management interface.

公开(公告)号：US09575919B2

公开(公告)日：2017-02-21

申请号：US14373911

申请日：2013-09-25

Applicant: HITACHI, LTD.

Inventor： Hirotoshi Akaike ,  Katsuya Tanaka ,  Makio Mizuno

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42 ,  G06F3/06 ,  G06F13/14 ,  G06F13/362

CPC classification number: G06F13/4027 ,  G06F3/06 ,  G06F13/14 ,  G06F13/362 ,  G06F13/4022 ,  G06F13/4282

Abstract: In a storage device applying PCIe to a back-end network connection, in order to be capable of allocating bus numbers and making a PCIe switch expanded afterwards usable, it is necessary to once reset all PCIe switches. To dissolve this necessity, PCIe switches of the back-end network of the storage device are connected in series, a range of continuous bus numbers that are managed and stored in bus number management table is allocated for the back-end network connection, and when expanding the PCIe switch, the bus numbers are allocated in ascending order from a minimum value of the allocatable bus numbers to each of a link between the PCIe switches and to a virtual PCI bus within the PCIe switch, and the bus numbers are allocated in descending order from a maximum value of the allocatable bus numbers to the link between the PCIe switch and a drive.

Abstract translation: 在将PCIe应用于后端网络连接的存储设备中，为了能够分配总线编号并使PCIe交换机之后扩展成可用，需要一次复位所有PCIe交换机。 为了解决这个需要，存储设备的后端网络的PCIe交换机被串联连接，被管理和存储在总线号码管理表中的连续总线数量被分配给后端网络连接，当 扩展PCIe交换机，总线编号从可分配总线数的最小值到PCIe交换机之间的链路和PCIe交换机中的虚拟PCI总线之间的每个升序分配，总线编号按降序分配 从可分配总线编号的最大值到PCIe开关和驱动器之间的链接。

公开(公告)号：US20130232297A1

公开(公告)日：2013-09-05

申请号：US13850972

申请日：2013-03-26

Applicant: HITACHI, LTD.

Inventor： Katsuya Tanaka ,  Kentaro Shimada

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0601 ,  G06F2003/0694 ,  G06F2212/1036 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract translation: 使用闪速存储器的存储系统包括存储控制器和作为存储介质的多个闪存模块。 每个闪速存储器模块包括至少一个闪速存储器芯片和用于调平属于闪存芯片的块的擦除计数的存储器控​​制器。 存储控制器将多个闪存模块组合成第一逻辑组，将用于访问属于第一逻辑组的闪存模块的第一地址转换为用于处理存储控制器中的第一地址的第二地址，并将 多个第一逻辑组转换成第二逻辑组。

公开(公告)号：US12045507B2

公开(公告)日：2024-07-23

申请号：US17691162

申请日：2022-03-10

Applicant: Hitachi, Ltd.

Inventor： Yutaro Kobayashi ,  Katsuya Tanaka ,  Hideaki Fukuda ,  Yoshikazu Murayama

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1668

Abstract: Each storage controller comprises a first storage unit, an interface unit, and a processing unit which sends, to the interface unit, a parameter which instructs n-fold write of writing data in each of n-number of (n is a natural number of 2 or more) other storage controllers. When the interface unit receives the parameter, the interface unit executes each processing of acquiring the data from the first storage unit and storing the data in the second storage unit, generating n-number of requests of writing the data in each of n-number of the other storage controllers, storing each of the generated requests in n-number of the queues corresponding to each of n-number of the other storage controllers, and processing each request stored in each queue and transferring the data stored in the second storage unit to each of n-number of the other storage controllers.

公开(公告)号：US10789196B2

公开(公告)日：2020-09-29

申请号：US16524375

申请日：2019-07-29

Applicant: Hitachi, Ltd.

Inventor： Katsuya Tanaka ,  Kentaro Shimada ,  Akira Yamamoto ,  Sadahiro Sugimoto

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.

公开(公告)号：US10459791B2

公开(公告)日：2019-10-29

申请号：US15545451

申请日：2015-02-26

Applicant: Hitachi, Ltd.

Inventor： Katsuya Tanaka ,  Makio Mizuno

IPC: G06F11/07 ,  G06F11/10 ,  G06F16/172 ,  G06F16/182 ,  G06F13/10 ,  G06F3/06

Abstract: A storage device according to an embodiment of the present invention has a plurality of storage nodes, each of which has a plurality of logical ports having send and receive queues for a communication request and an identification number, and an internal network for connecting the plurality of storage nodes with one another. The storage nodes each have, as the logical ports, a data communication logical port used for data communication with other storage nodes and an error communication logical port used to notify the other storage nodes of a state of the data communication logical port. When detecting an occurrence of transition of the data communication logical port to an error state, the storage node uses the error communication logical port to notify the other storage nodes of the identification number and the state of the data communication logical port.

公开(公告)号：US09703744B2

公开(公告)日：2017-07-11

申请号：US14650996

申请日：2013-01-23

Applicant: Hitachi, Ltd.

Inventor： Katsuya Tanaka ,  Masanori Takada ,  Naoya Okada

IPC: G06F13/40 ,  G06F13/42 ,  G06F11/14 ,  G06F13/38

CPC classification number: G06F13/4081 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2213/0026 ,  G06F2213/3802 ,  G06F2213/3804

Abstract: In a storage subsystem adopting HDD and PCIe-SSD as storage media, as a method for preventing the complication of having to select a removal method while considering the drive type inserted to the drive slot since the method for removing the HDD differs from the method for removing the PCIe-SSD according to the prior art, the present invention provides an LED for displaying whether it is possible to remove the HDD or the PCIe-SSD inserted to the slot of a drive enclosure, wherein when an HDD is inserted in the drive slot, the LED displays that removal of the HDD is enabled when power supply to the HDD is stopped, and when PCIe-SSD is inserted to the drive slot, the LED displays that removal of the SSD is enabled when Downstream Port Containment (DPC) is triggered in the downstream port of the PCIe switch to which the SSD is connected.