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公开(公告)号：US12124712B2
公开(公告)日：2024-10-22
申请号：US18179563
申请日：2023-03-07
申请人： Hitachi, Ltd.
发明人： Naoya Okada , Kentaro Shimada , Yuki Kotake , Yukiyoshi Takamura
IPC分类号： G06F3/06
CPC分类号： G06F3/0625 , G06F3/0655 , G06F3/0679
摘要： A storage system includes a storage controller and a plurality of storage drives. The storage controller holds power management information for managing power supplied to the storage system and power consumption of an operating mounted device of the storage system, and definition information for defining a relationship between power states and power consumption of the plurality of storage drives. The storage controller determines a power budget that can be supplied to the plurality of storage drives, based on the power management information according to a change in a configuration of the storage system, and determines a power state of each of the plurality of storage drives based on the power budget and the definition information.
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公开(公告)号：US11816336B2
公开(公告)日：2023-11-14
申请号：US18083653
申请日：2022-12-19
申请人： Hitachi, Ltd.
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0608 , G06F3/0638 , G06F3/0658 , G06F3/0688
摘要： The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.
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公开(公告)号：US11640265B2
公开(公告)日：2023-05-02
申请号：US17462549
申请日：2021-08-31
申请人： Hitachi, Ltd.
摘要： To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.
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公开(公告)号：US11256585B2
公开(公告)日：2022-02-22
申请号：US16821562
申请日：2020-03-17
申请人： Hitachi, Ltd.
IPC分类号： G06F11/00 , G06F11/20 , G06F11/07 , G06F11/30 , G06F9/4401 , G06F1/24 , G06F9/54 , G06F12/06 , G06F12/0873 , G06F9/50
摘要： A storage system includes a first storage controller including a plurality of main storage media and one or more processor cores, and a second storage controller including a plurality of main storage media and one or more processor cores and performing communication with the first storage controller. Storage areas of the main storage media in the first storage controller are allocated to an address map. In response to the occurrence of failures in one or mode main storage media of the main storage media of the first storage controller, the first storage controller performs restarting to reallocate the storage areas of the main storage media excluding one or more main storage media having caused the failures to an address map reduced than before the occurrence of the failures. The second storage controller continues operating during the restarting of the first storage controller.
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公开(公告)号：US10789196B2
公开(公告)日：2020-09-29
申请号：US16524375
申请日：2019-07-29
申请人： Hitachi, Ltd.
摘要： Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.
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公开(公告)号：US10732872B2
公开(公告)日：2020-08-04
申请号：US16329570
申请日：2017-02-27
申请人： HITACHI, LTD.
摘要： Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.
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公开(公告)号：US20200159605A1
公开(公告)日：2020-05-21
申请号：US16560308
申请日：2019-09-04
申请人： Hitachi, Ltd.
发明人： Kentaro Shimada , Makio Mizuno
摘要： It is detected whether write data has been correctly transmitted to a storage device under a protocol for directly connecting the storage device to a processor. An information processing system including: a processor; a memory; and a storage device, the processor first transmitting to the storage device, a command to invalidate data in a data area and which is designated by a write command, the storage device invalidating the data, the processor second transmitting to the storage device, the write command to write the data into the data area, and the storage device writing the data into the data area in accordance with the write command, validating the data in a data area into which the storage device has been successful in writing the data, and maintaining the data invalidated in a data area into which the storage device has failed in writing the data.
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公开(公告)号：US10402361B2
公开(公告)日：2019-09-03
申请号：US15959675
申请日：2018-04-23
申请人： Hitachi, Ltd.
摘要： Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.
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公开(公告)号：US12130752B2
公开(公告)日：2024-10-29
申请号：US18120827
申请日：2023-03-13
申请人： Hitachi, Ltd.
发明人： Kentaro Shimada , Masanori Takada
IPC分类号： G06F12/1081 , G06F13/24
CPC分类号： G06F12/1081 , G06F13/24
摘要： A protocol chip transmits the request from the host apparatus to a first processor through a first address translation unit. A first processor transmits a response to the request from the host apparatus, to the protocol chip through the first address translation unit. When the first processor stops processing, an instruction to transmit the request from the host apparatus to a second processor is transmitted to the protocol chip. When receiving the instruction to transmit the request from the host apparatus to the second processor, the protocol chip transmits the request from the host apparatus to the second processor through a second address translation unit. The second processor transmits the response to the request from the host apparatus to the protocol chip through the second address translation unit.
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公开(公告)号：US11829600B2
公开(公告)日：2023-11-28
申请号：US17689078
申请日：2022-03-08
申请人： Hitachi, Ltd.
IPC分类号： G06F3/06
CPC分类号： G06F3/0608 , G06F3/064 , G06F3/0673
摘要： A storage system includes an interface and a data compression system configured to compress reception data from the interface before the data is stored in a storage device. The data compression system is configured to compress the reception data using a first compression algorithm to generate first compressed data, use the number of appearances of each of predetermined code categories included in the first compressed data to estimate a decompression time when a second compression algorithm is used, select a second compression method including compression using the second compression algorithm when the decompression time is equal to or less than a threshold value, and select a first compression method that does not include the compression using the second compression algorithm when the decompression time is greater than the threshold value.
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