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公开(公告)号：US20140103287A1
公开(公告)日：2014-04-17
申请号：US14046984
申请日：2013-10-06
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
IPC: H01L45/00
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.
Abstract translation: 公开了一种半导体存储装置及其制造方法。 存储装置具有：基板; 衬底上的第一个字线; 第一层叠体，位于第一字线上方，并且具有N + 1个第一栅极间绝缘层和N个第一半导体层交替层叠; 位于所述层叠体上方并沿与所述第一字线相交的方向延伸的第一位线; 在所述第一栅极绝缘层和所述第一半导体层的侧表面上的第一栅极绝缘层; 在所述第一栅极绝缘层的侧表面上的第一沟道层; 以及在第一沟道层的侧表面上的第一可变电阻材料层。 第一可变电阻材料层在第一字线和第一位线相交的区域中。 多晶硅二极管用作选择元件。
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公开(公告)号：US09361978B2
公开(公告)日：2016-06-07
申请号：US14421822
申请日：2012-09-20
Applicant: Hitachi, Ltd.
Inventor： Nobuhiro Shiramizu , Satoru Hanzawa , Akira Kotabe
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/003 , G11C2013/0071 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1233 , H01L45/144
Abstract: The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series.A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).
Abstract translation: 提供本发明，以通过串联连接多个存储单元而获得的半导体存储器件中的每一层抑制提供给存储元件的电流不变化。 根据本发明的半导体存储器件包括串联连接在第一信号线和第二信号线之间的多个存储器单元，并分别向包括在存储器单元中的选择晶体管中的至少两个提供不同的栅极电压（参见 至图2）。
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公开(公告)号：US20150221367A1
公开(公告)日：2015-08-06
申请号：US14421822
申请日：2012-09-20
Applicant: Hitachi, Ltd.
Inventor： Nobuhiro Shiramizu , Satoru Hanzawa , Akira Kotabe
IPC: G11C13/00
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/003 , G11C2013/0071 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1233 , H01L45/144
Abstract: The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series.A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).
Abstract translation: 提供本发明，以通过串联连接多个存储单元而获得的半导体存储器件中的每一层抑制提供给存储元件的电流不变化。 根据本发明的半导体存储器件包括串联连接在第一信号线和第二信号线之间的多个存储器单元，并分别向包括在存储器单元中的选择晶体管中的至少两个提供不同的栅极电压（参见 至图2）。
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公开(公告)号：US11410774B2
公开(公告)日：2022-08-09
申请号：US16224431
申请日：2018-12-18
Applicant: HITACHI, LTD.
Inventor： Daisuke Suzuki , Satoru Hanzawa
Abstract: A computer system supplies a health service using body information measured by a measurement instrument. The computer system includes a computer that includes an analysis unit analyzing memory of a user. The analysis unit analyzes an error pattern based on a history of a matching-determination process for body information transmitted by the measurement instrument and body information input by the user, calculates a first evaluation value for evaluating a cognitive function based on an analysis result of the error pattern, analyzes an action pattern related to an input action of body information of the user, calculates a second evaluation value for evaluating the cognitive function based on an analysis result of the action pattern, and evaluates the cognitive function of the user based on the first evaluation value and the second evaluation value.
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公开(公告)号：US09385320B2
公开(公告)日：2016-07-05
申请号：US14857217
申请日：2015-09-17
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
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Patent Agency Ranking
公开(公告)号：US09153775B2
公开(公告)日：2015-10-06
申请号：US14468513
申请日：2014-08-26
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
Abstract translation: 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。
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公开(公告)号：US08841646B2
公开(公告)日：2014-09-23
申请号：US14046984
申请日：2013-10-06
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.
Abstract translation: 公开了一种半导体存储装置及其制造方法。 存储装置具有：基板; 衬底上的第一个字线; 第一层叠体，位于第一字线上方，并且具有N + 1个第一栅极间绝缘层和N个第一半导体层交替层叠; 位于所述层叠体上方并沿与所述第一字线相交的方向延伸的第一位线; 在所述第一栅极绝缘层和所述第一半导体层的侧表面上的第一栅极绝缘层; 在所述第一栅极绝缘层的侧表面上的第一沟道层; 以及在第一沟道层的侧表面上的第一可变电阻材料层。 第一可变电阻材料层在第一字线和第一位线相交的区域中。 多晶硅二极管用作选择元件。
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公开(公告)号：US09478284B2
公开(公告)日：2016-10-25
申请号：US14783846
申请日：2013-05-20
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Hiroyuki Minemura , Kenzo Kurotsuchi , Seiji Miura , Satoru Hanzawa
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/1233
Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).
Abstract translation: 本发明的目的是提供一种半导体存储器件，其能够通过在大电流通过存储器链的同时抑制电压降并行执行读取操作并且通过减少数字来减小芯片面积来增加读取传送速率 的外围电路供电。 根据本发明的半导体存储器件包括平板形状的上电极和下电极，分别在第一和第二方向上延伸的第一和第二选择晶体管，以及布置在第一选择晶体管和第二选择晶体管之间的布线， 通过关闭第一选择晶体管（参见图2），下电极被配置为彼此电绝缘。
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公开(公告)号：US09111605B2
公开(公告)日：2015-08-18
申请号：US14070131
申请日：2013-11-01
Applicant: Hitachi, Ltd.
Inventor： Satoru Hanzawa
CPC classification number: G11C7/22 , G11C7/1039 , G11C7/1042 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2207/2209 , G11C2207/2245 , G11C2211/5623 , G11C2211/5624
Abstract: A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region; the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver perform rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.
Abstract translation: 半导体存储装置提供具有高速运行，低电流和高可靠性的大容量相变存储器。 在存储器区域控制电路中激活读出启动信号的期间，并且读出驱动器对的块在上部存储区域中进行验证读取; 激活存储器区域控制电路中的写入使能信号，并且读出锁存器和写入驱动器对的块对下部存储器区域中的数据执行重写操作。 这种类型的操作允许通过在一个存储器区域中执行验证读取同时在其他存储器区域中执行时分重写来消除验证读取所需的时间和时分写入操作所需的时间，以实现更高的 可靠性重写操作以及抑制重写操作峰值电流。
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公开(公告)号：US20140361241A1
公开(公告)日：2014-12-11
申请号：US14468513
申请日：2014-08-26
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
Abstract translation: 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。
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