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    Power module and power converter
    1.
    发明授权
    Power module and power converter 有权

    公开(公告)号：US10692860B2

    公开(公告)日：2020-06-23

    申请号：US16217398

    申请日：2018-12-12

    Applicant: HITACHI, LTD.

    Inventor： Ryuusei Fujita ,  Kumiko Konishi ,  Akio Shima

    IPC: H01L27/06 ,  H03K17/12 ,  H01L27/02 ,  H01L29/423 ,  H03K17/082 ,  H03K17/16

    Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.

    Semiconductor device and method of manufacturing semiconductor device
    2.
    发明授权
    Semiconductor device and method of manufacturing semiconductor device 有权

    公开(公告)号：US10332997B2

    公开(公告)日：2019-06-25

    申请号：US16167982

    申请日：2018-10-23

    Applicant: HITACHI, LTD.

    Inventor： Shintaroh Sato ,  Masahiro Masunaga ,  Akio Shima

    IPC: H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L27/092 ,  H01L29/423

    Abstract: There is provided a semiconductor device that improves reliability. The impurity concentrations of a p++ source region and a p++ drain region are 5×1020 cm−3 or more. The channel-region-side end portion of a first insulating film is disposed on a p+ source region. The end portion has an inclined surface where the first insulating film thickness is reduced from the p+ source region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a p+ drain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the p+ drain region toward the channel region. A gate electrode is disposed on the channel region, the p+ source region, the p+ drain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.

    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
    4.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20140361241A1

    公开(公告)日：2014-12-11

    申请号：US14468513

    申请日：2014-08-26

    Applicant: Hitachi, Ltd.

    Inventor： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikatsu Takaura

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    Abstract translation: 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权

    公开(公告)号：US20220376109A1

    公开(公告)日：2022-11-24

    申请号：US17642811

    申请日：2020-06-18

    Applicant: Hitachi, Ltd. ,  TOYO TANSO CO., LTD

    Inventor： Keisuke Kobayashi ,  Kumiko Konishi ,  Akio Shima ,  Norihito Yabuki ,  Yusuke Sudoh ,  Satoru Nogami ,  Makoto Kitabatake

    IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L21/04

    Abstract: To provide a technique capable of improving performance and reliability of a semiconductor device. An n−-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p+-type body region (14), n+-type current spreading regions (16, 17), and a trench. TR are formed in the n−-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p+-type body region (14), a side surface S1 of the trench TR is in contact with the n+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n−-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench. Furthermore, an angle θ1 at which the upper surface T1 of the n−-type epitaxial layer (12) is inclined with respect to the side surface S1 is smaller than an angle θ2 at which the upper surface T1 of the n−-type epitaxial layer (12) is inclined with respect to the side surface S2.

    Semiconductor device and method for manufacturing same
    6.
    发明授权
    Semiconductor device and method for manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US09490247B2

    公开(公告)日：2016-11-08

    申请号：US14914883

    申请日：2013-08-29

    Applicant: HITACHI, LTD.

    Inventor： Hiroyuki Yoshimoto ,  Akio Shima ,  Digh Hisamoto

    IPC: H01L29/74 ,  H01L21/332 ,  H01L27/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L21/8249

    CPC classification number: H01L27/0623 ,  H01L21/2253 ,  H01L21/8249 ,  H01L29/0619 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/78

    Abstract: An IGBT (50) includes a p+ collector region (3) and an n−− drift region (1), in which a first transistor (TR1) and a second transistor (TR2) are formed on the n−− drift region (1). In the n−− drift region (1), a p-type hole extraction region (14) is formed in contact with the second transistor (TR2). When the IGBT (50) is in an on-state, electrons and holes flow through the first transistor (TR1), but a current does not flow through the second transistor (TR2). On the other hand, when the IGBT (50) is switched from the on-state to an off-state, holes flow through the first transistor (TR1), and holes flow through the hole extraction region (14) and the second transistor (TR2).

    Abstract translation: IGBT（50）包括p +集电极区（3）和n漂移区（1），其中在漂移区（1）上形成第一晶体管（TR1）和第二晶体管（TR2） ）。 在n漂移区域（1）中，形成与第二晶体管（TR2）接触的p型空穴提取区域（14）。 当IGBT（50）处于导通状态时，电子和空穴流过第一晶体管（TR1），但电流不流过第二晶体管（TR2）。 另一方面，当IGBT（50）从导通状态切换到断开状态时，空穴流过第一晶体管（TR1），空穴流过空穴取出区域（14）和第二晶体管（ TR2）。

    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
    7.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20160005969A1

    公开(公告)日：2016-01-07

    申请号：US14857217

    申请日：2015-09-17

    Applicant: Hitachi, Ltd.

    Inventor： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikatsu Takaura

    IPC: H01L45/00

    CPC classification number: H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    Abstract translation: 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

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