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1.发明授权Apparatus and method for reducing the number of rename registers required in the operation of a processor 失效用于减少处理器操作所需的重命名寄存器的数量的装置和方法
公开(公告)号：US6061777A
公开(公告)日：2000-05-09
申请号：US959646
申请日：1997-10-28
CPC分类号： G06F9/3863 , G06F9/384
摘要： One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.
摘要翻译： 本发明的一个方面涉及一种用于操作处理器的方法。 在本发明的一个版本中，该方法包括发送指令的步骤; 确定由发送的指令所针对的架构寄存器的目前架构化的RMAP条目; 选择与包含调度指令的操作数的物理寄存器相关联的RMAP条目; 更新所选RMAP条目中的使用指示符; 确定发送的指令是否可中断; 以及如果所分派的指令是不间断的，则更新当前架构的RMAP条目中的架构指示符和历史指示符。
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公开(公告)号：US20060294356A1
公开(公告)日：2006-12-28
申请号：US11168757
申请日：2005-06-27
IPC分类号： G06F9/00
CPC分类号： G06F9/44573
摘要： Apparatuses and methods of an executable-in-place solid-state device are disclosed. In one embodiment, a solid-state device includes a flash memory coupled to a dynamic random access memory, the dynamic random access memory to store at least as much data as the flash memory; and a logic circuit coupled to the flash memory and the dynamic access memory to copy data from the flash memory to the dynamic random access memory on power up of a data processing system coupled to the solid-state device. The logic circuit is to minimize writes to the flash memory by using the dynamic access memory as a working memory during operation of the data processing system, and/or to block at least some sectors of at least one of the flash memory and the dynamic random access memory when the data processing system uses the working memory to conserve power usage of the solid-state device.
摘要翻译： 公开了可执行就地固态设备的装置和方法。 在一个实施例中，固态设备包括耦合到动态随机存取存储器的闪速存储器，动态随机存取存储器至少存储与闪速存储器相同的数据; 以及耦合到闪速存储器和动态访问存储器的逻辑电路，用于在耦合到固态设备的数据处理系统上电时将数据从闪速存储器复制到动态随机存取存储器。 逻辑电路是通过在数据处理系统的操作期间使用动态存取存储器作为工作存储器来最小化对闪速存储器的写入，和/或阻止闪存和动态随机的至少一个的至少一些扇区 当数据处理系统使用工作存储器来节省固态设备的功率使用时，存取存储器。
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3.发明授权Method and system for executing a program within a multiscalar processor by processing linked thread descriptors 失效通过处理链接线程描述符来执行多级数据处理器内程序的方法和系统公开(公告)号：US06212542B1
公开(公告)日：2001-04-03
申请号：US08767487
申请日：1996-12-16
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/30087 , G06F9/3009 , G06F9/3851
摘要： A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected instruction set architecture. Each of the plurality of threads has a single entry point and a plurality of possible exit points. The multiscalar program further comprises thread code including a plurality of data structures that are each associated with a respective one of the plurality of threads. According to the method, a third data structure among the plurality of data structures is supplied to the thread scheduler. The third data structure, which is associated with a third thread among the plurality of threads, specifies a first data structure associated with a first possible exit point of the third thread and a second data structure associated with a second possible exit point of the third thread. The third thread is assigned to a selected one of the plurality of processing elements for execution. Prior to completing execution of the third thread, the thread scheduler selects from among the first and the second possible exit points of the third thread. In response to the selection, a corresponding one of the first and second data structures is loaded into the thread scheduler for processing.
摘要翻译： 提供了一种在具有多个处理元件和线程调度器的多级数值处理器内执行多级计算机的多级数据处理器和方法。 多节目程序包括多个线程，每个线程由所选择的指令集架构的一个或多个指令组成。 多个线程中的每一个具有单个入口点和多个可能的出口点。 多节目程序还包括线程代码，其包括多个数据结构，每个数据结构与多个线程中的相应一个线程相关联。 根据该方法，将多个数据结构中的第三数据结构提供给线程调度器。 与多个线程中的第三线程相关联的第三数据结构指定与第三线程的第一可能退出点相关联的第一数据结构和与第三线程的第二可能出口点相关联的第二数据结构 。 第三线程被分配给用于执行的多个处理元件中的所选择的一个。 在完成第三线程的执行之前，线程调度器从第三线程的第一和第二可能出口点中选择。 响应于该选择，第一和第二数据结构中相应的一个被加载到线程调度器中进行处理。
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4.发明授权Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order 失效用于构建包括无序线程和处理器的程序的方法和系统以及执行无序线程的方法
公开(公告)号：US5913925A
公开(公告)日：1999-06-22
申请号：US767490
申请日：1996-12-16
CPC分类号： G06F9/4843 , G06F9/44
摘要： A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.
摘要翻译： 提供了一种用于构建程序的方法和系统。 根据该方法，将多个指令中的每一个分配给多个线程中的至少一个。 多个线程包括第一，第二和第三线程，其中第三线程遵循第一线程并且以逻辑程序顺序在第二线程之前。 然后构建与第一线程相关联的数据结构。 数据结构包括在开始执行第三线程之前要启动第二线程的执行的指示。 根据一个实施例，数据结构内的指示是指定与第二线程相关联的第二数据结构的指针。
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5.发明授权Method and system for constructing a program including a navigation instruction 失效用于构建包括导航指令的程序的方法和系统
公开(公告)号：US5887166A
公开(公告)日：1999-03-23
申请号：US767491
申请日：1996-12-16
CPC分类号： G06F9/4881
摘要： A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the method, a plurality of threads are provided that each include at least one control flow instruction. From one or more control flow instructions within the plurality of threads, a condition upon which execution of a particular thread depends is determined. In response to the determination, at least one navigation instruction executable by the thread scheduler is created that indicates that the particular thread is to be assigned to one of the processing elements for execution in response to the condition.
摘要翻译： 提供了一种方法和系统，用于构建可由包括用于执行线程的一个或多个处理元件和用于将线程分配给处理元件以执行的线程调度器的处理器执行的程序。 根据该方法，提供多个线程，每个线程包括至少一个控制流程指令。 从多个线程内的一个或多个控制流程指令，确定特定线程的执行所依赖的状态。 响应于该确定，创建可由线程调度器执行的至少一个导航指令，其指示将特定线程分配给响应于条件执行的一个处理元件。
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6.发明授权Method and apparatus for dynamic allocation of registers for intermediate floating-point results 失效用于中间浮点数结果的寄存器的动态分配方法和装置
公开(公告)号：US5805916A
公开(公告)日：1998-09-08
申请号：US758017
申请日：1996-11-27
CPC分类号： G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3875
摘要： The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit. In one version, the execution unit includes a first stage which generates an intermediate result from the data according to an instruction; a means for providing a first portion of the intermediate result to an intermediate register; a means for providing a second portion of the intermediate result to a rename register associated with the instruction; a means for passing the first portion from the intermediate register to a second stage of the execution unit; a means for passing the second portion from the rename register to the second stage of the execution unit; wherein the second stage of the execution unit operates on the first and second portions according to the instruction.
摘要翻译： 本发明涉及一种多级执行单元，用于在微处理器中执行指令，该微处理器具有用于存储执行结果的多个重命名寄存器，用于存储指令的指令高速缓存，每个指令与重命名寄存器相关联，定序器单元用于提供指令 以及用于向执行单元提供数据的数据高速缓存。 在一个版本中，执行单元包括根据指令从数据生成中间结果的第一阶段; 用于将中间结果的第一部分提供给中间寄存器的装置; 用于将中间结果的第二部分提供给与指令相关联的重命名寄存器的装置; 用于将第一部分从中间寄存器传递到执行单元的第二级的装置; 用于将第二部分从重命名寄存器传递到执行单元的第二级的装置; 其中执行单元的第二级根据该指令在第一和第二部分上操作。
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7.发明授权Processor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetch 失效用于使用单个指令提取来执行分支指令和相关联的目标指令的处理器和方法
公开(公告)号：US5764940A
公开(公告)日：1998-06-09
申请号：US757186
申请日：1996-11-27
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3802
摘要： A processor and method of executing instructions within a processor are disclosed, which permit both a branch instruction and a target instruction of the branch instruction to be executed in response to a single instruction fetch. In accordance with an illustrative embodiment, the processor, which has an associated memory, simultaneously fetches a plurality of instructions from the memory. Branch instructions among the plurality of instructions are then detected. In response to a detection of a branch instruction among the plurality of instructions, a determination is made whether a target instruction to be executed in response to execution of the branch instruction is one of the plurality of instructions. In response to a determination that the target instruction is one of the plurality of instructions, the processor executes the target instruction without making an additional instruction fetch.
摘要翻译： 公开了一种在处理器内执行指令的处理器和方法，其允许响应于单个指令提取来执行转移指令的分支指令和目标指令。 根据说明性实施例，具有关联存储器的处理器同时从存储器中取出多个指令。 然后检测多个指令之间的分支指令。 响应于多个指令中的分支指令的检测，确定响应于分支指令的执行而执行的目标指令是否是多个指令之一。 响应于目标指令是多个指令之一的确定，处理器执行目标指令而不进行附加指令提取。
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8.发明授权Generation of unique address alias for memory disambiguation buffer to avoid false collisions 失效生成内存消歧缓冲区的唯一地址别名，以避免错误的冲突
公开(公告)号：US5897666A
公开(公告)日：1999-04-27
申请号：US762791
申请日：1996-12-09
CPC分类号： G06F9/3834 , G06F9/3855
摘要： A method and device for generating address aliases corresponding to memory locations, for avoiding false load/store collisions during memory disambiguation. The alias generator takes advantage of the fact that the entire address range will most likely not be active in the registers at any one time. The subset of the address range that is active can be represented with a smaller number of bits and, hence, the computation of true dependencies is greatly reduced. The address alias generator includes an array for receiving the memory addresses, comparators having inputs connected to each array entry and having outputs connected to an alias encoder, and a control logic unit for writing the given memory address in one of the entries. The output of a given gate is turned on if a memory address is the same as the contents of one of the entry corresponding to that output, and the control means is activated if the output of all of the gates are turned off. In the preferred embodiment, the memory addresses are 32-bit values, the array has 64 entries, and the encoder generates 6-bit values for the address aliases. The processor includes a memory disambiguation buffer for identifying load/store collisions, that uses the 6-bit address aliases.
摘要翻译： 一种用于生成对应于存储器位置的地址别名的方法和装置，用于在存储器消除歧义期间避免虚假加载/存储冲突。 别名生成器利用这样一个事实，即整个地址范围在任何一个时刻很可能不会在寄存器中被激活。 活动的地址范围的子集可以用较少的比特数来表示，因此真正的依赖关系的计算大大减少。 地址别名生成器包括用于接收存储器地址的阵列，具有连接到每个阵列条目并具有连接到别名编码器的输出的输入的比较器，以及用于在给定存储器地址之一中写入给定存储器地址的控制逻辑单元。 如果存储器地址与对应于该输出的条目中的一个的内容相同，则给定门的输出被打开，并且如果所有门的输出被关闭，则控制装置被激活。 在优选实施例中，存储器地址是32位值，该阵列具有64个条目，编码器为地址别名生成6位值。 处理器包括用于识别加载/存储冲突的内存消歧缓冲器，其使用6位地址别名。
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9.发明授权Processor and method for out-of-order completion of floating-point operations during load/store multiple operations 失效用于在加载/存储多个操作期间浮点运算的无序完成的处理器和方法
公开(公告)号：US5850563A
公开(公告)日：1998-12-15
申请号：US526610
申请日：1995-09-11
申请人： Albert J. Loper , Soummya Mallick
发明人： Albert J. Loper , Soummya Mallick
CPC分类号： G06F9/30043 , G06F9/3838 , G06F9/3863
摘要： A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit loads or stores data to or from the general purpose registers, and the microprocessor's dispatch unit dispatches instructions to a plurality of execution units, including the load/store execution unit and the floating point execution unit. The method comprises the dispatch unit dispatching a multi-register instruction to the load/store unit to begin execution of the multi-register instruction, wherein the multi-register instruction, such as a store multiple or a load multiple, stores or loads data from more than one of the plurality of general purpose registers to memory, and further, prior to the multi-register instruction finishing execution in the load/store unit, the dispatch unit dispatches a floating-point instruction, which is dependent upon source operand data stored in one or more floating-point registers of the plurality of floating point registers, to the floating-point execution unit, wherein the dispatched floating-point instruction completes execution prior to the multi-register instruction finishing execution.
摘要翻译： 提供了在先前加载/存储多个指令之前的超标量微处理器中用于早期完成浮点指令的方法和装置。 微处理器的加载/存储执行单元向通用寄存器加载或存储数据，微处理器的调度单元将指令分派到包括加载/存储执行单元和浮点执行单元的多个执行单元。 该方法包括：调度单元向加载/存储单元分配多寄存器指令以开始执行多寄存器指令，其中多寄存器指令（例如存储器多个或加载倍数）存储或加载来自 多个通用寄存器中的多于一个存储器，此外，在多个寄存器指令在加载/存储单元中完成执行之前，调度单元调度浮点指令，其依赖于存储的源操作数据 在多个浮点寄存器的一个或多个浮点寄存器中，提供给浮点执行单元，其中调度浮点指令在多寄存器指令完成执行之前完成执行。
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10.发明授权Method and system for emulating instructions by performing an operation directly using special-purpose register contents 失效通过直接使用专用寄存器内容进行操作来仿真指令的方法和系统
公开(公告)号：US5758140A
公开(公告)日：1998-05-26
申请号：US581793
申请日：1996-01-25
申请人： James Allan Kahle , Soummya Mallick
发明人： James Allan Kahle , Soummya Mallick
CPC分类号： G06F9/30167 , G06F9/30174
摘要： A system and method for improving the performance of a processor that emulates a guest instruction where the guest instruction includes a first and second operand. The first operand is stored in a general purpose register, and the second operand is stored in a special-purpose register. The method and system provides a host instruction that performs an operation using the first operand and the second operand without moving the second operand from the special-purpose register into the general purpose register. This reduces the number of instructions in the semantic routines necessary to operate on immediate data from guest instructions and increases emulation performance.
摘要翻译： 一种用于提高仿真访客指令的处理器的性能的系统和方法，其中所述访客指令包括第一和第二操作数。 第一个操作数存储在通用寄存器中，第二个操作数存储在专用寄存器中。 该方法和系统提供主机指令，其使用第一操作数和第二操作数执行操作，而不将第二操作数从专用寄存器移动到通用寄存器中。 这减少了从客户指令对即时数据进行操作所需的语义程序中的指令数量，并增加了仿真性能。
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