公开(公告)号：US20150355272A1

公开(公告)日：2015-12-10

申请号：US13153472

申请日：2011-06-06

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G01R31/28 ,  G01R31/30

CPC classification number: G01R31/2884 ,  G01R31/3004 ,  G11C5/00 ,  G11C5/005 ,  G11C11/1673 ,  G11C11/1677 ,  G11C29/50008 ,  G11C29/52 ,  H01F1/00 ,  H01L21/00

Abstract: Integrated circuit comprising a sensing unit that includes a sensing circuit, two conductors and a magnetic storage element. The sensing circuit monitors a voltage drop across the element when a current is passed between the conductors with the element in between. The voltage drop is pre-calibrated to indicate a change in conductivity in the element that is caused by an external magnetic field. Advantageously, this indication is usable particularly for assessing a possible data corruption in a magnetic memory circuit in the integrated circuit, due to stray and external magnetic fields. Methods of using the sensing unit are also proposed.

Abstract translation: 集成电路包括感测单元，其包括感测电路，两个导体和磁存储元件。 当电流在导体之间通过元件之间时，感测电路监测元件两端的电压降。 电压降被预校准，以指示由外部磁场引起的元件中的电导率的变化。 有利地，该指示特别用于评估由于杂散和外部磁场而导致的集成电路中的磁存储器电路中可能的数据损坏。 还提出了使用感测单元的方法。

公开(公告)号：US09105569B2

公开(公告)日：2015-08-11

申请号：US13214107

申请日：2011-08-19

Applicant: Krishnakumar Mani ,  Benjamin Chen

Inventor： Krishnakumar Mani ,  Benjamin Chen

IPC: H01L43/12 ,  H01L27/22

CPC classification number: H01L27/222 ,  H01L22/26 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A method for fabricating a magnetic film structure is provided. The method comprises forming a magnetic structure on a bottom electrode layer, the magnetic structure comprising at least one pinned bottom magnetic film layer having a fixed magnetic orientation; at least one top magnetic film layer whose magnetic orientation can be manipulated by a current; and a tunneling layer between the bottom magnetic film layer and the top magnetic film layer; forming a metallic hard mask atop the magnetic structure; patterning and etching the metallic hard mask to define exposed areas of the magnetic structure; selectively etching the exposed areas of the magnetic structure by a chemical etch process based on a CO etch chemistry to form discrete magnetic bits.

Abstract translation: 提供一种制造磁性膜结构的方法。 该方法包括在底部电极层上形成磁性结构，所述磁性结构包括至少一个具有固定磁性取向的固定底部磁性薄膜层; 至少一个磁性取向可由电流操纵的顶部磁性膜层; 以及在底部磁性膜层和顶部磁性膜层之间的隧道层; 在磁性结构上形成金属硬掩模; 图案化和蚀刻金属硬掩模以限定磁结构的暴露区域; 通过基于CO蚀刻化学的化学蚀刻工艺来选择性地蚀刻磁性结构的暴露区域以形成离散磁性位。

公开(公告)号：US08913069B2

公开(公告)日：2014-12-16

申请号：US12706694

申请日：2010-02-16

Applicant: Krishnakumar Mani ,  Jay Kamdar

Inventor： Krishnakumar Mani ,  Jay Kamdar

IPC: G06T1/60 ,  G06F13/14 ,  G09G5/39 ,  G09G5/00

CPC classification number: G09G5/00 ,  G09G2300/0857

Abstract: In one embodiment there is provided, a display driver system, comprising, at least one display driver; a magnetic random access memory (MRAM) macro; and a display driver interface coupling the MRAM macro and the at least one display driver.

Abstract translation: 在一个实施例中，提供了一种显示驱动器系统，包括：至少一个显示驱动器; 磁性随机存取存储器（MRAM）宏; 以及耦合所述MRAM宏和所述至少一个显示驱动器的显示驱动器接口。

公开(公告)号：US08320175B2

公开(公告)日：2012-11-27

申请号：US12714401

申请日：2010-02-26

Applicant: Krishnakumar Mani ,  Jannier Maximo Roiz Wilson ,  Kimihiro Satoh

Inventor： Krishnakumar Mani ,  Jannier Maximo Roiz Wilson ,  Kimihiro Satoh

IPC: G11C11/14

CPC classification number: H01L27/222 ,  G11C11/1659 ,  G11C11/1675

Abstract: Disclosed is a nonvolatile magnetic memory cell, comprising: a) a switchable magnetic element; b) a word line and a bit line to energize the switchable magnetic element; and c) a magnetic field boosting material positioned adjacent to at least one of the word line and the bit line to boost a magnetic field generated by current flowing therein.

Abstract translation: 公开了一种非易失性磁存储单元，包括：a）可切换磁性元件; b）字线和位线，以激励可切换的磁性元件; 以及c）与所述字线和所述位线中的至少一个相邻定位的磁场增强材料，以增加在其中流动的电流产生的磁场。

公开(公告)号：US20120087180A1

公开(公告)日：2012-04-12

申请号：US12901845

申请日：2010-10-11

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/00

CPC classification number: G11C11/165 ,  G11C5/06 ,  G11C11/161 ,  G11C11/1659

Abstract: A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit.

Abstract translation: 一种半导体集成电路，包括用于低电压操作的第一电路区域和用于高电压操作的第二电路区域。 电路区域包括由金属间电介质（IMD）隔开的两个垂直堆叠的后端图案化金属层。 两个金属层和IMD形成在低电压下可操作的组合。 第一电路区域使用组合的第一部分在低电压下操作，并且第二电路区域使用组合的第二部分以高电压路由，第二部分中的两个金属层通过IMD互连通过IMD互连 通孔，用于承受高电压。 第一部分可以包括磁性随机存取存储器（MRAM）装置的阵列，并且第二电路区域可以包括显示驱动电路。

公开(公告)号：US20090067231A1

公开(公告)日：2009-03-12

申请号：US12184224

申请日：2008-07-31

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/14

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08

Abstract: Embodiments of the invention magnetic memory device, comprising: a magnetic tunnel junction (MTJ) which includes a first free layer optimized for reading; and a second free layer separate from the MTJ and optimized for writing.

Abstract translation: 本发明的磁存储器件的实施例包括：磁性隧道结（MTJ），其包括为阅读而优化的第一自由层; 和第二自由层与MTJ分离并优化用于写入。

公开(公告)号：US09395410B2

公开(公告)日：2016-07-19

申请号：US13153472

申请日：2011-06-06

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G01R27/08 ,  G01R31/28 ,  G01R31/30 ,  G11C5/00 ,  H01F1/00 ,  H01L21/00

CPC classification number: G01R31/2884 ,  G01R31/3004 ,  G11C5/00 ,  G11C5/005 ,  G11C11/1673 ,  G11C11/1677 ,  G11C29/50008 ,  G11C29/52 ,  H01F1/00 ,  H01L21/00

Abstract: Integrated circuit comprising a sensing unit that includes a sensing circuit, two conductors and a magnetic storage element. The sensing circuit monitors a voltage drop across the element when a current is passed between the conductors with the element in between. The voltage drop is pre-calibrated to indicate a change in conductivity in the element that is caused by an external magnetic field. Advantageously, this indication is usable particularly for assessing a possible data corruption in a magnetic memory circuit in the integrated circuit, due to stray and external magnetic fields. Methods of using the sensing unit are also proposed.

Abstract translation: 集成电路包括感测单元，其包括感测电路，两个导体和磁存储元件。 当电流在导体之间通过元件之间时，感测电路监测元件两端的电压降。 电压降被预校准，以指示由外部磁场引起的元件中的电导率的变化。 有利地，该指示特别用于评估由于杂散和外部磁场而导致的集成电路中的磁存储器电路中可能的数据损坏。 还提出了使用感测单元的方法。

公开(公告)号：US08879306B2

公开(公告)日：2014-11-04

申请号：US13208577

申请日：2011-08-12

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/00

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/08

Abstract: Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.

Abstract translation: 存储器电路包括可寻址磁隧道结（MTJ）堆叠，在电路中形成磁存储元件。 MTJ堆叠包括在自由层和固定层之间的隧道氧化物层。 应力诱导层邻近自由层设置以向自由层提供拉伸或压缩应力，以便操纵将位写入MTJ堆叠所需的磁场。 还提出了使用存储器电路的方法。

公开(公告)号：US20140301138A1

公开(公告)日：2014-10-09

申请号：US13153473

申请日：2011-06-06

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/14 ,  H01L29/82 ,  H01L21/8239

CPC classification number: G11C11/1673 ,  G11C11/14 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/36 ,  H01L27/222 ,  H01L27/224 ,  H01L27/228 ,  H01L29/872 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.

Abstract translation: 存储单元包括两个导体，在两个导体之间具有串联连接的磁存储元件和肖特基二极管。 肖特基二极管在两个导体之间提供一个单向的导电路径，并通过该元件。 肖特基二极管形成在两个导体中的一个中的金属层和经处理的接合层之间。 还公开了用于存储器单元的处理和操作的方法。 使用肖特基二极管的存储单元可以设计用于高速运行和高密度集成。 有利地，接合层也可以用作硬掩模，用于限定存储单元中的各个磁存储元件。 存储单元对磁性随机存取存储器（MRAM）电路特别有用。

公开(公告)号：US08835101B1

公开(公告)日：2014-09-16

申请号：US13155299

申请日：2011-06-07

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G03F7/26

CPC classification number: G03F7/2024 ,  G03F7/26 ,  H01L21/0274 ,  H01L21/033

Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.

Abstract translation: 一种制造电路的方法，通过在衬底上限定第一组抗蚀剂特征并对应于第一掩模布局，随后在对应于第二掩模布局的衬底上限定第二组抗蚀剂特征，其中第二组增加 到第一组，以纠正任一掩码布局中的错误。 在另一方面，该方法是通过在衬底上限定第一组抗蚀剂特征并对应于具有误差的第一掩模布局，蚀刻衬底，同时第一组保护所选择的区域，在第二组抗蚀剂特征上限定第二组抗蚀剂特征 衬底并且对应于第二掩模布局，随后蚀刻衬底以选择性地去除所选择的区域的部分以纠正误差。