利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.037 秒)

    Systems and methods for coexistence between plurality of wireless communications modules sharing single antenna
    1.
    发明授权
    Systems and methods for coexistence between plurality of wireless communications modules sharing single antenna 有权
    共享单个天线的多个无线通信模块之间共存的系统和方法

    公开(公告)号：US09130605B2

    公开(公告)日：2015-09-08

    申请号：US12625613

    申请日：2009-11-25

    申请人： Hong-Kai Hsu ,  Yuan-Hung Chung ,  Hsien-Chyi Chiou ,  Wei Wang ,  Wen-Ying Chien ,  Jwo-An Lin ,  I-Lin Hsieh

    发明人： Hong-Kai Hsu ,  Yuan-Hung Chung ,  Hsien-Chyi Chiou ,  Wei Wang ,  Wen-Ying Chien ,  Jwo-An Lin ,  I-Lin Hsieh

    IPC分类号： H04B1/44 ,  H04B1/00 ,  H04W72/12 ,  H04W88/06

    CPC分类号： H04B1/006 ,  H04W72/1215 ,  H04W88/06

    摘要： A system for the coexistence between a plurality of wireless communications modules sharing single antenna is provided. A wireless communications chipset includes a first wireless communications module configured to transmit or receive first wireless communications signals, and a second wireless communications module configured to transmit or receive second wireless communications signals. A path selection circuit is configured to connect the first wireless communications module to the antenna via a first transceiving path or a second transceiving path for transmitting and receiving the first wireless signals according to transceiving statuses of the first wireless signals and the second wireless signals.

    摘要翻译： 提供了一种用于共享单个天线的多个无线通信模块之间共存的系统。 无线通信芯片组包括被配置为发送或接收第一无线通信信号的第一无线通信模块以及被配置为发送或接收第二无线通信信号的第二无线通信模块。 路径选择电路被配置为经由第一收发路径或第二收发路径将第一无线通信模块连接到天线，用于根据第一无线信号和第二无线信号的收发状态发送和接收第一无线信号。

    SYSTEMS AND METHODS FOR COEXISTENCE BETWEEN PLURALITY OF WIRELESS COMMUNICATIONS MODULES SHARING SINGLE ANTENNA
    2.
    发明申请
    SYSTEMS AND METHODS FOR COEXISTENCE BETWEEN PLURALITY OF WIRELESS COMMUNICATIONS MODULES SHARING SINGLE ANTENNA 有权
    无线通信模块共享单个天线之间的共同体系和方法

    公开(公告)号：US20110009074A1

    公开(公告)日：2011-01-13

    申请号：US12625613

    申请日：2009-11-25

    申请人： Hong-Kai Hsu ,  Yuan-Hung Chung ,  Hsien-Chyi Chiou ,  Wei Wang ,  Wen-Ying Chien ,  Jwo-An Lin ,  I-Lin Hsieh

    发明人： Hong-Kai Hsu ,  Yuan-Hung Chung ,  Hsien-Chyi Chiou ,  Wei Wang ,  Wen-Ying Chien ,  Jwo-An Lin ,  I-Lin Hsieh

    IPC分类号： H04B1/44

    CPC分类号： H04B1/006 ,  H04W72/1215 ,  H04W88/06

    摘要： A system for the coexistence between a plurality of wireless communications modules sharing single antenna is provided. A wireless communications chipset includes a first wireless communications module configured to transmit or receive first wireless communications signals, and a second wireless communications module configured to transmit or receive second wireless communications signals. A path selection circuit is configured to connect the first wireless communications module to the antenna via a first transceiving path or a second transceiving path for transmitting and receiving the first wireless signals according to transceiving statuses of the first wireless signals and the second wireless signals.

    摘要翻译： 提供了一种用于共享单个天线的多个无线通信模块之间共存的系统。 无线通信芯片组包括被配置为发送或接收第一无线通信信号的第一无线通信模块以及被配置为发送或接收第二无线通信信号的第二无线通信模块。 路径选择电路被配置为经由第一收发路径或第二收发路径将第一无线通信模块连接到天线，用于根据第一无线信号和第二无线信号的收发状态发送和接收第一无线信号。

    Buffer control method and device thereof
    7.
    发明授权
    Buffer control method and device thereof 有权
    缓冲控制方法及其装置

    公开(公告)号：US07836231B2

    公开(公告)日：2010-11-16

    申请号：US11798279

    申请日：2007-05-11

    申请人： I-Lin Hsieh ,  Chun-Yuan Su

    发明人： I-Lin Hsieh ,  Chun-Yuan Su

    IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F12/00

    CPC分类号： H04L49/9078 ,  H04L49/90 ,  H04L49/9042

    摘要： A buffer control method for controlling packets to be stored in a buffer having a data region and a command queue region. First, the number of the packets that can be stored in the data buffer is determined. Then, a count value representing the remained capacity of the data region is updated. Finally, the count value and a value of maximum data length are compared to determine whether to increase the number of the packets that can be stored in the buffer.

    摘要翻译： 一种用于控制要存储在具有数据区域和命令队列区域的缓冲器中的分组的缓冲器控制方法。 首先，确定可以存储在数据缓冲器中的数据包的数量。 然后，更新表示数据区域的剩余容量的计数值。 最后，比较计数值和最大数据长度的值，以确定是否增加可以存储在缓冲区中的数据包数量。

    METHOD AND SYSTEM FOR INITIALIZING DEVICES
    8.
    发明申请
    METHOD AND SYSTEM FOR INITIALIZING DEVICES 有权
    用于初始化设备的方法和系统

    公开(公告)号：US20080126783A1

    公开(公告)日：2008-05-29

    申请号：US11610631

    申请日：2006-12-14

    申请人： Chun-Yuan Su ,  I-Lin Hsieh ,  Chi-Feng Lin

    发明人： Chun-Yuan Su ,  I-Lin Hsieh ,  Chi-Feng Lin

    IPC分类号： G06F15/177

    CPC分类号： G06F1/24

    摘要： A system for a first device to initialize a second device is disclosed. The initialization bus is coupled between the first device and the second device. During an initialization period, the first device triggers at least one transmission command through the initialization bus to transmit at least one initial value to the second device via the initialization bus.

    摘要翻译： 公开了一种用于初始化第二设备的第一设备的系统。 初始化总线耦合在第一设备和第二设备之间。 在初始化期间，第一设备通过初始化总线触发至少一个发送命令，以经由初始化总线将至少一个初始值发送到第二设备。

    Chip testing methods and chips
    9.
    发明申请
    Chip testing methods and chips 有权
    芯片测试方法和芯片

    公开(公告)号：US20060107137A1

    公开(公告)日：2006-05-18

    申请号：US11147736

    申请日：2005-06-08

    申请人： I-Lin Hsieh

    发明人： I-Lin Hsieh

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31725

    摘要： Testing methods and chips preventing sampling errors caused by asynchronous effect. The chip comprises a first logic portion driven by a first clock signal with a first operating frequency, and a second logic portion driven by a second clock signal with a second operating frequency. The first operating frequency is higher than the second operating frequency, and is not an integral multiple of the second operating frequency. In the test method, a third operating frequency of a third clock signal is generated according to the second clock signal, in which the third operating frequency is higher than the first operating frequency and is an integral multiple of the second operating frequency. The first clock signal is replaced by the third clock signal and the first logic portion is tested by the third clock signal. The second logic portion is tested by the second clock signal.

    摘要翻译： 测试方法和芯片防止异步效应引起的采样错误。 芯片包括由具有第一工作频率的第一时钟信号驱动的第一逻辑部分和由具有第二工作频率的第二时钟信号驱动的第二逻辑部分。 第一工作频率高于第二工作频率，而不是第二工作频率的整数倍。 在测试方法中，根据第二时钟信号产生第三时钟信号的第三工作频率，其中第三工作频率高于第一工作频率，并且是第二工作频率的整数倍。 第一时钟信号由第三时钟信号代替，第一逻辑部分被第三时钟信号测试。 第二逻辑部分由第二时钟信号测试。

    Buffer control method and device thereof
    10.
    发明申请
    Buffer control method and device thereof 有权
    缓冲控制方法及其装置

    公开(公告)号：US20080022021A1

    公开(公告)日：2008-01-24

    申请号：US11798279

    申请日：2007-05-11

    申请人： I-Lin Hsieh ,  Chun-Yuan Su

    发明人： I-Lin Hsieh ,  Chun-Yuan Su

    IPC分类号： G06F3/00

    CPC分类号： H04L49/9078 ,  H04L49/90 ,  H04L49/9042

    摘要： A buffer control method for controlling packets to be stored in a buffer having a data region and a command queue region. First, the number of the packets that can be stored in the data buffer is determined. Then, a count value representing the remained capacity of the data region is updated. Finally, the count value and a value of maximum data length are compared to determine whether to increase the number of the packets that can be stored in the buffer.

    摘要翻译： 一种用于控制要存储在具有数据区域和命令队列区域的缓冲器中的分组的缓冲器控制方法。 首先，确定可以存储在数据缓冲器中的数据包的数量。 然后，更新表示数据区域的剩余容量的计数值。 最后，比较计数值和最大数据长度的值，以确定是否增加可以存储在缓冲区中的数据包数量。