Error correction system using an iterative product code
    1.
    发明授权
    Error correction system using an iterative product code 有权
    纠错系统使用迭代产品代码

    公开(公告)号:US09048879B1

    公开(公告)日:2015-06-02

    申请号:US13586710

    申请日:2012-08-15

    IPC分类号: H03M13/29 H04L1/00

    摘要: An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.

    摘要翻译: 纠错系统包括使用交织分量代码和嵌入奇偶校验分量代码的迭代代码。 在一些实施例中,在传输侧,在输入节点处接收的输入信号基于交织的代码进行编码,该代码编码输入数据的交错版本以产生第一组码字。 第一组码字的至少一部分优选地被划分为多个符号,这些符号基于嵌入的奇偶校验码被编码以提供编码数据。 类似地,在一些实施例中,在接收侧,检测所接收的数据以产生检测到的信息和软输出。 检测到的信息根据嵌入的奇偶校验码进行解码以获得解码的信息。 解码的信息优选地与其他软信息一起被交织的解码器使用以产生用于偏置随后的解码迭代的可靠性度量。

    Error correction system using an iterative product code
    2.
    发明授权
    Error correction system using an iterative product code 有权
    纠错系统使用迭代产品代码

    公开(公告)号:US08255763B1

    公开(公告)日:2012-08-28

    申请号:US11937389

    申请日:2007-11-08

    IPC分类号: H03M13/00

    摘要: An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. On the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. A portion of the first set of codewords is divided into a plurality of symbols which are encoded based on the embedded parity code. On the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information is used with other soft information by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.

    摘要翻译: 纠错系统包括使用交织分量代码和嵌入奇偶校验分量代码的迭代代码。 在发送侧,在输入节点处接收的输入信号基于交织代码进行编码,该代码对输入数据的交织版本进行编码以产生第一组码字。 第一组码字的一部分被分成多个符号,这些符号是基于嵌入的奇偶校验码进行编码的。 在接收侧,检测接收到的数据以产生检测信息和软输出。 检测到的信息根据嵌入的奇偶校验码进行解码以获得解码的信息。 经解码的信息与交织的解码器的其他软信息一起使用以产生用于偏置随后的解码迭代的可靠性度量。

    Multi-viterbi receive channel decoder
    3.
    发明授权
    Multi-viterbi receive channel decoder 有权
    多维特比接收信道解码器

    公开(公告)号:US08090059B1

    公开(公告)日:2012-01-03

    申请号:US11799488

    申请日:2007-05-01

    IPC分类号: H03D1/00 H04L27/06

    摘要: A detector includes Viterbi detectors. A first Viterbi detector generates a preliminary decision signal. A second Viterbi detector generates a final decision signal based on an input data signal and the preliminary decision signal. The second Viterbi detector is arranged in series with the first Viterbi detector.

    摘要翻译: 检测器包括维特比检测器。 第一维特比检测器产生初步判定信号。 第二维特比检测器基于输入数据信号和初步判定信号产生最终判定信号。 第二维特比检测器与第一维特比检测器串联布置。

    Defect detection design
    4.
    发明授权
    Defect detection design 有权
    缺陷检测设计

    公开(公告)号:US08054717B1

    公开(公告)日:2011-11-08

    申请号:US11907676

    申请日:2007-10-16

    IPC分类号: G11B15/52

    摘要: A system and method are provided to detect defects in a data storage medium by sampling data read from the data storage medium. Time referenced samples of data read from the data storage medium are equalized to mediate the effects of channel noise and the equalized samples are decoded by a decoder, such as a Viterbi decoder. The decoded signal is then reconstructed through a reconstruction filter to approximate the equalized signal. The equalized data signal and the reconstructed data signal are then combined and compared in a bit-by-bit deconstruction scheme to determine, based on a variation between the signal elements, that a defect exists on the data storage medium. Additional action is then taken to mediate the effects of attempting to process corrupted data based on the defect by isolating the defective bit.

    摘要翻译: 提供了一种系统和方法,用于通过对从数据存储介质读取的数据进行采样来检测数据存储介质中的缺陷。 将从数据存储介质读取的数据的时间参考样本相等以调解信道噪声的影响,并且均衡样本由诸如维特比解码器之类的解码器解码。 然后通过重建滤波器重建经解码的信号以近似均衡的信号。 然后将均衡的数据信号和重建的数据信号以逐位解构方案进行组合和比较,以基于信号元素之间的变化来确定数据存储介质上存在缺陷。 然后采取额外的行动来通过隔离有缺陷的位来调解基于缺陷来处理被破坏的数据的效果。

    Circuits, architectures, apparatuses, systems, algorithms and methods and software for amplitude drop detection
    5.
    发明授权
    Circuits, architectures, apparatuses, systems, algorithms and methods and software for amplitude drop detection 有权
    用于幅度下降检测的电路,架构,设备,系统,算法和方法以及软件

    公开(公告)号:US08027378B1

    公开(公告)日:2011-09-27

    申请号:US11818079

    申请日:2007-06-12

    IPC分类号: H04B3/46 H04B17/00 H04Q1/20

    CPC分类号: H04B3/46 H04L1/0054 H04L1/20

    摘要: Methods, circuits, systems, and networks for detecting an amplitude drop in an incoming signal. The methods generally comprise sampling the incoming signal at regular intervals to produce a plurality of sample values, producing a plurality of drop flags in response to the plurality of sample values, and detecting the amplitude drop in response to at least two of the drop flags. The circuits generally comprise a sampling circuit configured to produce a sample signal in response to the incoming signal, a threshold circuit configured to receive the sample signal and to produce a drop flag signal in response to the sample signal, and a drop detection circuit configured to produce an amplitude drop signal in response to at least two values of the drop flag signal. The systems and networks generally comprise the present circuits and/or any circuit embodying the inventive concepts described herein. The present invention advantageously provides for detection of amplitude drops in an incoming signal, operating in the digital (rather than analog) domain. Embodiments of the present invention also reduce the incidence of “false positives” due to transient low amplitudes. Correct detection of amplitude drops can improve the accuracy of signal decoders.

    摘要翻译: 用于检测输入信号中的幅度下降的方法,电路,系统和网络。 所述方法通常包括以规则的间隔对输入信号进行采样以产生多个采样值,响应于多个采样值产生多个下降标志,以及响应于至少两个下降标志来检测幅度下降。 电路通常包括采样电路,其被配置为响应于输入信号产生采样信号;阈值电路,被配置为接收采样信号并响应于采样信号产生降幅标志信号;以及丢弃检测电路,被配置为 响应于液滴标志信号的至少两个值产生幅度下降信号。 系统和网络通常包括本发明的电路和/或体现本文所描述的发明概念的任何电路。 本发明有利地提供了在数字(而不是模拟)域中操作的输入信号中的幅度下降的检测。 本发明的实施例还降低了由于瞬时低振幅引起的“假阳性”的发生率。 正确检测幅度可以提高信号解码器的精度。

    Defect detection design
    6.
    发明授权
    Defect detection design 有权
    缺陷检测设计

    公开(公告)号:US08315132B1

    公开(公告)日:2012-11-20

    申请号:US13235658

    申请日:2011-09-19

    IPC分类号: G11B15/52

    摘要: A system and method are provided to detect defects in a data storage medium by sampling data read from the data storage medium. Time referenced samples of data read from the data storage medium are equalized to mediate the effects of channel noise and the equalized samples are decoded by a decoder, such as a Viterbi decoder. The decoded signal is then reconstructed through a reconstruction filter to approximate the equalized signal. The equalized data signal and the reconstructed data signal are then combined and compared in a bit-by-bit deconstruction scheme to determine, based on a variation between the signal elements, that a defect exists on the data storage medium. Additional action is then taken to mediate the effects of attempting to process corrupted data based on the defect by isolating the defective bit.

    摘要翻译: 提供了一种系统和方法,用于通过对从数据存储介质读取的数据进行采样来检测数据存储介质中的缺陷。 将从数据存储介质读取的数据的时间参考样本相等以调解信道噪声的影响,并且均衡样本由诸如维特比解码器之类的解码器解码。 然后通过重建滤波器重建经解码的信号以近似均衡的信号。 然后将均衡的数据信号和重建的数据信号以逐位解构方案进行组合和比较,以基于信号元素之间的变化来确定数据存储介质上存在缺陷。 然后采取额外的行动来通过隔离有缺陷的位来调解基于缺陷来处理被破坏的数据的效果。

    Multi-Viterbi receive channel decoder
    7.
    发明授权
    Multi-Viterbi receive channel decoder 有权
    多维特比接收信道解码器

    公开(公告)号:US08594246B1

    公开(公告)日:2013-11-26

    申请号:US13335267

    申请日:2011-12-22

    IPC分类号: H03D1/00 H04L27/06

    摘要: A circuit includes a first Viterbi detector configured to generate a first estimate signal based on an equalized signal. The first estimate signal includes preliminary non-return-to-zero data estimates. A first filter is configured to generate a first filtered signal based on a preliminary decision signal. The preliminary decision signal is generated based on the first estimate signal. A second Viterbi detector is in communication with the first Viterbi detector. The second Viterbi detector is configured to generate a final decision signal based on a sum of (i) a delayed version of the equalized signal, and (ii) the first filtered signal, wherein the final decision signal comprises final non-return-to-zero estimates.

    摘要翻译: 电路包括第一维特比检测器,其经配置以基于均衡信号产生第一估计信号。 第一个估计信号包括初步的无归零数据估计。 第一滤波器被配置为基于初步判定信号产生第一滤波信号。 基于第一估计信号产生初步判定信号。 第二维特比检测器与第一维特比检测器通信。 第二维特比检测器被配置为基于(i)均衡信号的延迟版本和(ii)第一滤波信号的和产生最终判定信号,其中最终判决信号包括最终的不返回 - 零估计。

    Defect recovery for iteratively-decoded data channel
    8.
    发明授权
    Defect recovery for iteratively-decoded data channel 有权
    用于迭代解码数据通道的缺陷恢复

    公开(公告)号:US08122314B1

    公开(公告)日:2012-02-21

    申请号:US11936418

    申请日:2007-11-07

    IPC分类号: H03M13/00 H04L1/18 G06F11/00

    摘要: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by incorporating results from a previous decoding iteration. In one embodiment, a final multiplexer selects between the final detector output or a previous detector output based on the absence or presence of defective data. In another embodiment, the branch metrics for the defective data, which otherwise would be combined with a priori LLRs from an outer decoder of a prior stage, are ignored so that the a priori LLRs themselves are used alone. The two embodiments can be used together.

    摘要翻译: 在迭代解码中,数据恢复方案通过结合先前的解码迭代的结果来校正损坏的或有缺陷的数据。 在一个实施例中,最终多路复用器根据不存在或存在缺陷数据在最终检测器输出或先前检测器输出之间进行选择。 在另一个实施例中,将忽略否则将与来自前一级的外部解码器的先验LLR组合的缺陷数据的分支量度,以使得单独使用先验LLR本身。 两个实施例可以一起使用。

    Nonlinear viterbi complexity reduction
    9.
    发明授权
    Nonlinear viterbi complexity reduction 有权
    非线性维特比复杂度降低

    公开(公告)号:US07961797B1

    公开(公告)日:2011-06-14

    申请号:US11973150

    申请日:2007-10-05

    IPC分类号: H04K1/10

    摘要: System and methods for reducing the complexity or area of a non-linear Viterbi detector. In some embodiments, a Viterbi detector calculates branch metrics for a subset of the branches in a trellis diagram. This subset may be selected based on comparing an equalized signal with a signal level table of all the possible branches. These branch metrics may be calculated using high performance branch metric calculation techniques. The remaining branch metrics may be calculated based on the computed branch metrics using a technique that consumes fewer resources. The Viterbi detectors in the present invention may also be used in an iterative decoding scheme, where multiple detectors are cascaded. In these embodiments, a Viterbi detector may select a subset of the branches based on detection results from other Viterbi detectors.

    摘要翻译: 用于降低非线性维特比检测器的复杂度或面积的系统和方法。 在一些实施例中,维特比检测器在网格图中计算分支的子集的分支度量。 可以基于将均衡信号与所有可能分支的信号电平表进行比较来选择该子集。 这些分支度量可以使用高性能分支度量计算技术来计算。 可以使用消耗更少资源的技术,基于所计算的分支度量来计算剩余分支度量。 本发明中的维特比检测器也可以用于级联的多个检测器的迭代解码方案。 在这些实施例中,维特比检测器可以基于来自其他维特比检测器的检测结果来选择分支的子集。