摘要:
An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.
摘要:
An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. On the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. A portion of the first set of codewords is divided into a plurality of symbols which are encoded based on the embedded parity code. On the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information is used with other soft information by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.
摘要:
A system and method are provided to detect defects in a data storage medium by sampling data read from the data storage medium. Time referenced samples of data read from the data storage medium are equalized to mediate the effects of channel noise and the equalized samples are decoded by a decoder, such as a Viterbi decoder. The decoded signal is then reconstructed through a reconstruction filter to approximate the equalized signal. The equalized data signal and the reconstructed data signal are then combined and compared in a bit-by-bit deconstruction scheme to determine, based on a variation between the signal elements, that a defect exists on the data storage medium. Additional action is then taken to mediate the effects of attempting to process corrupted data based on the defect by isolating the defective bit.
摘要:
A system and method are provided to detect defects in a data storage medium by sampling data read from the data storage medium. Time referenced samples of data read from the data storage medium are equalized to mediate the effects of channel noise and the equalized samples are decoded by a decoder, such as a Viterbi decoder. The decoded signal is then reconstructed through a reconstruction filter to approximate the equalized signal. The equalized data signal and the reconstructed data signal are then combined and compared in a bit-by-bit deconstruction scheme to determine, based on a variation between the signal elements, that a defect exists on the data storage medium. Additional action is then taken to mediate the effects of attempting to process corrupted data based on the defect by isolating the defective bit.
摘要:
A detector includes Viterbi detectors. A first Viterbi detector generates a preliminary decision signal. A second Viterbi detector generates a final decision signal based on an input data signal and the preliminary decision signal. The second Viterbi detector is arranged in series with the first Viterbi detector.
摘要:
Methods, circuits, systems, and networks for detecting an amplitude drop in an incoming signal. The methods generally comprise sampling the incoming signal at regular intervals to produce a plurality of sample values, producing a plurality of drop flags in response to the plurality of sample values, and detecting the amplitude drop in response to at least two of the drop flags. The circuits generally comprise a sampling circuit configured to produce a sample signal in response to the incoming signal, a threshold circuit configured to receive the sample signal and to produce a drop flag signal in response to the sample signal, and a drop detection circuit configured to produce an amplitude drop signal in response to at least two values of the drop flag signal. The systems and networks generally comprise the present circuits and/or any circuit embodying the inventive concepts described herein. The present invention advantageously provides for detection of amplitude drops in an incoming signal, operating in the digital (rather than analog) domain. Embodiments of the present invention also reduce the incidence of “false positives” due to transient low amplitudes. Correct detection of amplitude drops can improve the accuracy of signal decoders.
摘要:
A circuit includes a first Viterbi detector configured to generate a first estimate signal based on an equalized signal. The first estimate signal includes preliminary non-return-to-zero data estimates. A first filter is configured to generate a first filtered signal based on a preliminary decision signal. The preliminary decision signal is generated based on the first estimate signal. A second Viterbi detector is in communication with the first Viterbi detector. The second Viterbi detector is configured to generate a final decision signal based on a sum of (i) a delayed version of the equalized signal, and (ii) the first filtered signal, wherein the final decision signal comprises final non-return-to-zero estimates.
摘要:
A channel decoder including an amplifier configured to amplify a signal; a first summer configured to generate an output signal based on the signal amplified by the amplifier; and a Viterbi detector module configured to, based on the output signal, generate a first estimate signal and a second estimate signal, wherein the first estimate signal and the second estimate signal respectively indicate an estimate of data in the signal. The channel decoder further includes a second summer configured to generate a first error signal indicating a first gradient based on the first estimate signal; and a third summer configured to generate a second error signal indicating a second error gradient based on the second estimate signal. The first summer is configured to generate the output signal based on (i) the first error signal and (ii) the second error signal.
摘要:
A detector includes a Viterbi module that generates a first preliminary data estimate signal and a second preliminary data estimate signal based on a received data signal. A first loop generates a first error signal based on said first preliminary data estimate signal. A second loop generates a second error signal based on the second preliminary data estimate signal.
摘要:
A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device.