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1.发明授权
公开(公告)号：US4150438A
公开(公告)日：1979-04-17
申请号：US815133
申请日：1977-07-13
CPC分类号： G06F13/4213 , G06F13/4027
摘要： An interface circuit for use in a data transmission system has a first port for connection to a 16 wire data highway of the type proposed by the I.E.C. (International Electrochemical Commission) for the interconnection of instruments, and a second port capable of being connected to an eight-wire or two-wire data link. The interface circuit includes an encoding circuit operative to encode at least some commands applied to the first port, and an enabling circuit for selectively enabling data applied to the data terminals of the first port and the encoded commands to pass to the second port. The interface circuit also includes status circuits for establishing statuses of the circuit in accordance with commands supplied thereto, including a status indicating that the interface has been addressed, and a circuit responsive to the absence of this "addressed" status to disable the enabling circuit, so as to prevent at least some of the encoded commands and the data received at the data terminals of the first port from being passed to the second port.
摘要翻译： 用于数据传输系统的接口电路具有用于连接到由I.E.C提出的类型的16线数据高速公路的第一端口。 （国际电化学委员会），用于互连仪器，以及能够连接到八线或二线数据链路的第二端口。 接口电路包括编码电路，其可操作以对施加到第一端口的至少一些命令进行编码;以及使能电路，用于选择性地使得施加到第一端口的数据终端的数据和编码的命令传递到第二端口。 接口电路还包括用于根据提供给它的命令来建立电路状态的状态电路，包括指示接口已被寻址的状态，以及响应于不存在该“寻址”状态以禁用使能电路的电路， 以防止在第一端口的数据终端处接收到的编码命令和数据中的至少一些被传递到第二端口。
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公开(公告)号：US4250407A
公开(公告)日：1981-02-10
申请号：US854282
申请日：1977-11-23
IPC分类号： H01L21/822 , G11C11/414 , G11C11/415 , H01L27/04 , H03K19/018 , H03K19/08 , H03K19/082 , H03K5/153 , H03K17/62
CPC分类号： G11C11/414 , G11C11/415 , H03K19/01806 , H03K19/0813 , H03K19/0823
摘要： A single patch on an integrated circuit is arranged to patch any one of four different logical states into the circuit, according to whether the pin is grounded, floating, coupled to a supply rail via a resistor, or coupled to the supply rail directly. In one embodiment, the voltage thresholds of three transistors are arranged so that they switch on successively in response to successively higher voltages on the patch pin, thereby controlling the binary logic signals at each of two output points in the circuit; in the other embodiment, multi-emitter transistors are arranged with differing current thresholds to achieve the same result.
摘要翻译： 集成电路上的单个贴片被布置为根据引脚是接地的，浮动的，通过电阻器耦合到电源轨，还是直接耦合到电源轨，将四种不同逻辑状态中的任何一种补偿到电路中。 在一个实施例中，三个晶体管的电压阈值被布置成使得它们响应于补丁引脚上的连续更高的电压而依次接通，从而在电路中的两个输出点的每一个处控制二进制逻辑信号; 在另一实施例中，多发射极晶体管被布置成具有不同的电流阈值以获得相同的结果。
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