Real-time network monitoring and security
    3.
    发明授权
    Real-time network monitoring and security 有权
    实时网络监控和安全性

    公开(公告)号:US08364833B2

    公开(公告)日:2013-01-29

    申请号:US10937540

    申请日:2004-09-10

    IPC分类号: G06F15/16

    摘要: There is provided a hardware device for monitoring and intercepting data packetized data traffic at full line rate. In preferred high bandwidth embodiments, full line rate corresponds to rates that exceed 100 Mbytes/s and in some cases 1000 Mbytes/s. Monitoring and intercepting software, alone, is not able to operate on such volumes of data in real-time. A preferred embodiment comprises: a data delay buffer (208) with multiple delay outputs (216); a search engine logic (210) for implementing a set of basic search tools that operate in real-time on the data traffic; a programmable gate array (206); an interface (212) for passing data quickly to software sub-systems; and control means for implementing software control of the operation of the search tools. The programmable gate array (206) inserts the data packets into the delay buffer (208), extracts them for searching at the delay outputs and formats and schedules the operation of the search engine logic (210). One preferred embodiment uses an IP co-processor as the search engine logic.

    摘要翻译: 提供了用于以全线速率监视和截取数据分组化数据业务的硬件设备。 在优选的高带宽实施例中,全线速率对应于超过100Mbytes / s且在某些情况下为1000Mbytes / s的速率。 单独监控和截取软件无法实时地对这些数据量进行操作。 优选实施例包括:具有多个延迟输出(216)的数据延迟缓冲器(208); 搜索引擎逻辑(210),用于实现在数据业务上实时操作的一组基本搜索工具; 可编程门阵列(206); 用于将数据快速传送到软件子系统的接口(212) 以及用于实现对搜索工具的操作的软件控制的控制装置。 可编程门阵列(206)将数据包插入到延迟缓冲器(208)中,提取它们用于在延迟输出处进行搜索并格式化并调度搜索引擎逻辑(210)的操作。 一个优选实施例使用IP协处理器作为搜索引擎逻辑。

    Real-time network monitoring and security
    4.
    发明申请
    Real-time network monitoring and security 有权
    实时网络监控和安全性

    公开(公告)号:US20050108573A1

    公开(公告)日:2005-05-19

    申请号:US10937540

    申请日:2004-09-10

    IPC分类号: H04L12/26 H04L29/06 G06F11/30

    摘要: There is provided a hardware device for monitoring and intercepting data packetized data traffic at full line rate. In preferred high bandwidth embodiments, full line rate corresponds to rates that exceed 100 Mbytes/s and in some cases 1000 Mbytes/s. Monitoring and intercepting software, alone, is not able to operate on such volumes of data in real-time. A preferred embodiment comprises: a data delay buffer (208) with multiple delay outputs (216); a search engine logic (210) for implementing a set of basic search tools that operate in real-time on the data traffic; a programmable gate array (206); an interface (212) for passing data quickly to software sub-systems; and control means for implementing software control of the operation of the search tools. The programmable gate array (206) inserts the data packets into the delay buffer (208), extracts them for searching at the delay outputs and formats and schedules the operation of the search engine logic (210). One preferred embodiment uses an IP co-processor as the search engine logic.

    摘要翻译: 提供了用于以全线速率监视和截取数据分组化数据业务的硬件设备。 在优选的高带宽实施例中,全线速率对应于超过100Mbytes / s且在某些情况下为1000Mbytes / s的速率。 单独监控和截取软件无法实时地对这些数据量进行操作。 优选实施例包括:具有多个延迟输出(216)的数据延迟缓冲器(208); 搜索引擎逻辑(210),用于实现在数据业务上实时操作的一组基本搜索工具; 可编程门阵列(206); 用于将数据快速传送到软件子系统的接口(212) 以及用于实现对搜索工具的操作的软件控制的控制装置。 可编程门阵列(206)将数据包插入到延迟缓冲器(208)中,提取它们用于在延迟输出处进行搜索并格式化并调度搜索引擎逻辑(210)的操作。 一个优选实施例使用IP协处理器作为搜索引擎逻辑。