公开(公告)号：US07085176B1

公开(公告)日：2006-08-01

申请号：US10771526

申请日：2004-02-04

申请人： Howard L. Levy ,  Nadeem N. Eleyan ,  Nayon Tomsio ,  Hong S. Kim

发明人： Howard L. Levy ,  Nadeem N. Eleyan ,  Nayon Tomsio ,  Hong S. Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/20

摘要： It has been discovered that initialization of a memory array can be improved by setting the nodes of the memory array to a predetermined value automatically upon applying power to the integrated circuit. Data input nodes and a memory write enable node are configured to store the predetermined values on the nodes of the memory array in response to successive enablement of word lines corresponding to the nodes of the memory array and automatic reset of the word lines. Circuitry included for initializing control and data signals of the memory array are effectively disabled upon termination of the initialization. Inclusion of circuitry that initiates and terminates the initialization obviates an additional input/output pin for this purpose.

摘要翻译： 已经发现，通过在对集成电路施加电力时将存储器阵列的节点自动设置为预定值，可以提高存储器阵列的初始化。 数据输入节点和存储器写使能节点被配置为响应于对应于存储器阵列的节点的字线的连续启用和字线的自动复位，将预定值存储在存储器阵列的节点上。 包括用于初始化存储器阵列的控制和数据信号的电路在初始化结束时被有效禁止。 启动和终止初始化的电路的包含为此避免了额外的输入/输出引脚。

公开(公告)号：US07036098B2

公开(公告)日：2006-04-25

申请号：US10610252

申请日：2003-06-30

申请人： Nadeem N. Eleyan ,  Harsh D. Sharma ,  Howard L. Levy ,  Hong S. Kim

发明人： Nadeem N. Eleyan ,  Harsh D. Sharma ,  Howard L. Levy ,  Hong S. Kim

IPC分类号： G06F17/50

CPC分类号： H03K5/04 ,  G01R31/3016 ,  G01R31/31725

摘要： Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

摘要翻译： 片上信号的信号状态持续时间（如脉冲宽度）通常对集成电路的成功运行至关重要。 通过片上技术测量的信号状态持续时间将信号状态持续时间信息提供给片上信号状态持续时间控制系统。 信号状态持续时间控制系统使用信息来调整片上信号的信号状态持续时间。 在一个实施例中，片上信号的信号状态持续时间是片上信号的脉冲宽度。 信号持续时间测量和调整系统例如可用于测量诸如自复位信号的状态持续时间，这些信号难以外部测量并使用片上技术来调整信号状态持续时间。

公开(公告)号：US07131034B2

公开(公告)日：2006-10-31

申请号：US10292329

申请日：2002-11-12

申请人： Nadeem N. Eleyan ,  Harsh D. Sharma ,  Howard L. Levy ,  Hong S. Kim

发明人： Nadeem N. Eleyan ,  Harsh D. Sharma ,  Howard L. Levy ,  Hong S. Kim

IPC分类号： G06F11/00

CPC分类号： G01R31/31725 ,  H03K5/26 ,  H03K2005/00058 ,  H03K2005/00156

摘要： A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time. The signal propagation time can be adjusted by inserting varying delay elements into the signal path traversed by test data signal. The signal duration measurement system can be fabricated on-chip, thus making its use more practical. The signal duration measurement system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure.

摘要翻译： 信号持续时间测量系统将测试数据信号的已知持续时间T 1与被测信号的状态的持续时间T 2进行比较。 在一个实施例中，如果T 2与T 1相比较好，则产生被测信号的电路“通过”。 否则被测信号“失败”，并且已经确定了一个问题。 此外，在一个实施例中，可以选择性地调整T 1以更准确地测量T 2。在一个实施例中，允许测试数据信号在信号的单个状态期间行进具有已知信号传播延迟时间的信号路径 被测试。 状态开始时的数据信号，例如， 在被测信号的上升期间，与在状态结束时捕获的数据信号进行比较。 在被测信号的坠落期间。 如果初始和捕获的数据信号相同，则被测信号的持续时间大于或等于信号传播延迟时间。 可以通过将变化的延迟元件插入由测试数据信号穿过的信号路径来调节信号传播时间。 信号持续时间测量系统可以片上制造，从而使其使用更加实用。 信号持续时间测量系统例如可用于测量难以外部测量的诸如自复位信号的信号的状态持续时间。

公开(公告)号：US07164612B1

公开(公告)日：2007-01-16

申请号：US10683636

申请日：2003-10-10

申请人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

发明人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/5004

摘要： Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. In designs susceptible to post-manufacture data dependent creep in a device characteristic, such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch. Typically, the techniques described herein may be employed to address sensing offsets that have developed post-manufacture due to a data-dependent effect. However, in some realizations, the techniques described herein may be used to address a sensing offset arising at least in part from other or additional sources.

摘要翻译： 可以至少部分地通过将感测放大器中的一对交叉耦合晶体管中的一个选择性地暴露于所选择的偏置电压以提供暴露的晶体管的特性的补偿偏移来提供用于感测偏移的制造后补偿 。 在易受设备特性的后制造数据依赖性蠕变的设计中，可以有利地通过使读出放大器感测到有选择地偏向所选择的主要值以引起补偿偏移的位置来提供这种曝光。 在一些实现中，使用片上测试块来识别和表征感测不匹配。 通常，本文描述的技术可以用于解决由于数据相关效应而在制造后开发的感测偏移。 然而，在一些实现中，本文描述的技术可以用于解决至少部分地从其他源或附加源产生的感测偏移。

公开(公告)号：US06574160B1

公开(公告)日：2003-06-03

申请号：US10074396

申请日：2002-02-11

申请人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

发明人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

IPC分类号： G11C702

CPC分类号： G11C7/04 ,  G11C7/065 ,  G11C2207/065

摘要： According to one embodiment, a memory is disclosed. The memory includes a differential sense amplifier that receives a data input and a complementary data input; and a switching mechanism, coupled to the amplifier, that switches the data input and the complementary data input to minimize a negative bias temperature instability (NBTI) effect on the amplifier.

摘要翻译： 根据一个实施例，公开了一种存储器。 存储器包括接收数据输入和补充数据输入的差分读出放大器; 以及耦合到放大器的切换机构，其切换数据输入和互补数据输入以最小化对放大器的负偏压温度不稳定性（NBTI）效应。

公开(公告)号：US06891403B2

公开(公告)日：2005-05-10

申请号：US10277566

申请日：2002-10-22

申请人： Harsh D. Sharma ,  Howard L. Levy ,  Hong Kim ,  Nadeem N. Eleyan

发明人： Harsh D. Sharma ,  Howard L. Levy ,  Hong Kim ,  Nadeem N. Eleyan

IPC分类号： G01R31/28 ,  H03L7/06 ,  G01R23/02

CPC分类号： H03L7/06 ,  G01R31/2882

摘要： The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.

摘要翻译： PLL的锁定频率用于通过各种锁存器件（触发器等）来锁存测试信号。 各种不同的延迟被选择性地应用于测试信号以提供延迟的测试信号，并且测量延迟的测试信号以确定测试信号中的延迟是否与PLL的锁定频率中的抖动相匹配。 当测试信号的延迟与PLL的锁定频率中的抖动匹配时，测试信号的相应延迟用于确定PLL的有效锁定频率。

公开(公告)号：US07020035B1

公开(公告)日：2006-03-28

申请号：US10683633

申请日：2003-10-10

申请人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

发明人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

IPC分类号： G11C7/02

CPC分类号： G11C29/026 ,  G11C7/02 ,  G11C7/06 ,  G11C11/41 ,  G11C29/02 ,  G11C29/028 ,  G11C2207/2254

摘要： Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. Such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, purposefully skewed values (e.g., value and value_1) are introduced directly into the sense amplifier. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch.

摘要翻译： 可以至少部分地通过将感测放大器中的一对交叉耦合晶体管中的一个选择性地暴露于所选择的偏置电压以提供暴露的晶体管的特性的补偿偏移来提供用于感测偏移的制造后补偿 。 这样的曝光可以有利地通过使感测放大器感测到有选择地偏向所选择的主要值以引起补偿偏移的原位来提供。 在一些实现中，有目的的偏斜值（例如，值和值1）被直接引入到读出放大器中。 在一些实现中，使用片上测试块来识别和表征感测不匹配。

公开(公告)号：US06762961B2

公开(公告)日：2004-07-13

申请号：US10123480

申请日：2002-04-16

申请人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

发明人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

IPC分类号： G11C700

CPC分类号： G11C7/04 ,  G11C7/065

摘要： Post-manufacture variation of timing may be employed to address data-dependent degradation or creep in device characteristics affecting a differential circuit. One particular example of such data-dependent degradation or creep involves Negative Bias Temperature Instability (NBTI). In certain memory circuit configurations, NBTI can cause threshold voltage (Vt) of PMOS devices to increase by an amount that depends on the historical amount of voltage bias that has been applied across gate and source/drain nodes. In the case of many sense amplifier designs, a predominant value read out using the sense amp may tend to disparately affect one device (or set of devices) as compared with an opposing device (or set of devices). In other words, if the same data value is read over and over again, then one of two opposing PMOS devices of a typical sense amp will accumulate an NBTI-related Vt shift, while the opposing PMOS device will accumulate little or no shift. The accumulated mismatch tends to cause an increase in the sense amp fail-point.

摘要翻译： 可以采用定时的制造后变化来解决影响差分电路的器件特性中与数据有关的退化或蠕变。 这种数据依赖性降解或蠕变的一个具体实例涉及负偏压温度不稳定性（NBTI）。 在某些存储器电路配置中，NBTI可以使PMOS器件的阈值电压（Vt）增加取决于施加在栅极和源极/漏极节点上的历史电压偏置量的量。 在许多读出放大器设计的情况下，与相对的设备（或一组设备）相比，使用感测放大器读出的主要值可能会不利地影响一个设备（或设备组）。 换句话说，如果一次又一次地读取相同的数据值，则典型读出放大器的两个相对的PMOS器件中的一个将累积NBTI相关的Vt移位，而相对的PMOS器件将积累很少或没有移位。 累积的不匹配趋于导致感测放大器故障点的增加。

公开(公告)号：US6144370A

公开(公告)日：2000-11-07

申请号：US834720

申请日：1997-04-01

申请人： Nadeem N. Eleyan ,  Stephen M. Bobbio

发明人： Nadeem N. Eleyan ,  Stephen M. Bobbio

IPC分类号： G06F3/038 ,  G06F17/30

CPC分类号： G06F3/03549 ,  G06F3/0383

摘要： A track ball control system which is attachable to a computer system that has a display screen on which a cursor is positionable, including at least one track ball regulator for providing physical control of the position of the track ball in response to signals from the control system. These signals depend on the location of the cursor on the display screen and cause the track ball to change in movement. This change in movement may be a vertical change, and/or an azimuthal change. The operator does not control this change in movement except indirectly by knowingly or unknowingly positioning the cursor in a position which causes the signals to be sent to the track ball.

摘要翻译： 轨道球控制系统，其可附接到具有可在其上定位光标的显示屏幕的计算机系统，包括至少一个轨道球调节器，用于响应于来自控制系统的信号提供轨道球的位置的物理控制 。 这些信号取决于光标在显示屏上的位置，导致轨迹球的移动变化。 这种运动变化可能是垂直变化和/或方位角变化。 操作者不会控制这种运动变化，除非有意或不知不觉将光标定位在导致信号发送到轨迹球的位置。