公开(公告)号：US6034956A

公开(公告)日：2000-03-07

申请号：US106960

申请日：1998-06-29

申请人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  Michael Hans Fisher ,  Joel Mark Gould ,  John David Jabusch ,  Arthur Robert Williams

发明人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  Michael Hans Fisher ,  Joel Mark Gould ,  John David Jabusch ,  Arthur Robert Williams

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04Q1/00 ,  G06F13/00 ,  H04L12/28 ,  H04M3/00 ,  H04M7/00

CPC分类号： H04Q11/0478 ,  H04L49/15 ,  H04L49/253 ,  H04L49/101 ,  H04L49/1523 ,  H04L49/205 ,  H04L49/254

摘要： The multi-stage interconnection network of the present invention includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

摘要翻译： 本发明的多级互连网络包括使用具有并行寻路能力的第一级中的交换机。 利用这些交换机，可以从其中通过网络到指定的目的地节点的多个路径并行尝试寻找其间的连接路径的任何一个节点启动定向闪存。 第一级和第二级中的开关互连，使得第一级中的每个开关与每个可能的优先级连接到第二级的开关。 并行路径寻找交换机和网络还被配置为通过组合监视所有连接来测试闪存洪泛的拒绝。

公开(公告)号：US5774067A

公开(公告)日：1998-06-30

申请号：US950104

申请日：1997-10-16

申请人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  Michael Hans Fisher ,  Joel Mark Gould ,  John David Jabusch ,  Arthur Robert Williams

发明人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  Michael Hans Fisher ,  Joel Mark Gould ,  John David Jabusch ,  Arthur Robert Williams

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04Q1/00

CPC分类号： H04Q11/0478 ,  H04L49/15 ,  H04L49/253 ,  H04L49/101 ,  H04L49/1523 ,  H04L49/205 ,  H04L49/254

摘要： A multi-stage interconnection network includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

摘要翻译： 多级互连网络包括使用具有并行路径寻找能力的第一级中的交换机。 利用这些交换机，可以从其中通过网络到指定的目的地节点的多个路径并行尝试寻找其间的连接路径的任何一个节点启动定向闪存。 第一级和第二级中的开关互连，使得第一级中的每个开关与每个可能的优先级连接到第二级的开关。 并行路径寻找交换机和网络还被配置为通过组合监视所有连接来测试闪存洪泛的拒绝。

公开(公告)号：US5835024A

公开(公告)日：1998-11-10

申请号：US481855

申请日：1995-06-07

申请人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  James William Feeney ,  Michael Hans Fisher ,  Eliezer Upfal ,  Arthur Robert Williams

发明人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  James William Feeney ,  Michael Hans Fisher ,  Eliezer Upfal ,  Arthur Robert Williams

IPC分类号： G06F15/173 ,  H03K17/04

CPC分类号： G06F15/17393

摘要： The present invention addresses the limitations of prior art ALLNODE switches by including dual priority, adaptive, path seeking, and flash-flood functionalities in a single ALLNODE switch. The switch of the present invention further includes a selection device responsive to a selection signal for enabling the selection of the mode of switch operation from any one of the foregoing functionalities. The selection signal is applied to the switch in a number of different ways including: the transmission of a command over the data path interface to the switch; the transmission of a command over special purpose serial or parallel control lines; or via hardwiring. Thus, the selection of functionality for the switch is capable of being made in either a dynamic or static fashion. The present invention further comprises two new high performance networks utilizing the selectable function ALLNODE switch. The networks have a different functionality being performed at each stage, and comprise a "Multi-Dilated Path Seeking Network" and a "Nested Path Seeking and Flash-Flood Network."

摘要翻译： 本发明通过在单个ALLNODE交换机中包括双重优先级，自适应，寻路和闪存功能来解决现有技术的ALLNODE交换机的局限性。 本发明的开关还包括响应于选择信号的选择装置，用于使得能够从前述功能中的任一个选择开关操作模式。 选择信号以多种不同的方式应用于交换机，包括：通过数据路径接口向交换机发送命令; 通过专用串行或并行控制线传输命令; 或通过硬连线。 因此，切换器的功能的选择能够以动态或静态方式进行。 本发明还包括利用可选功能ALLNODE开关的两个新的高性能网络。 网络具有在每个阶段执行的不同功能，并且包括“多扩展路径寻求网络”和“嵌套路径寻求和闪存洪泛网络”。

公开(公告)号：US06263374B1

公开(公告)日：2001-07-17

申请号：US08286107

申请日：1994-08-04

申请人： Howard Thomas Olnowich ,  Michael Wayland Dotson ,  James William Feeney ,  Michael Hans Fisher ,  John David Jabusch ,  Robert Francis Lusch ,  Michael Anthony Maniguet

发明人： Howard Thomas Olnowich ,  Michael Wayland Dotson ,  James William Feeney ,  Michael Hans Fisher ,  John David Jabusch ,  Robert Francis Lusch ,  Michael Anthony Maniguet

IPC分类号： G06F15173

CPC分类号： G06F15/17375 ,  G06F13/4022 ,  H04L49/101 ,  H04L49/15 ,  H04L49/253 ,  H04L49/30 ,  H04L49/508 ,  H04L49/555

摘要： An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

摘要翻译： 将标准处理器总线协议和架构（如MicroChannel总线）转换并适应于更渐进的交换机互连协议和架构的设备。 现有的基于总线的架构通过启用数千个处理器的互连来扩展到执行并行和集群功能。 该装置相对容易实现并且构建便宜。 通信媒体是基于交换机的，完全并行，支持由交换网络互连的节点。

公开(公告)号：US5742761A

公开(公告)日：1998-04-21

申请号：US800070

申请日：1997-02-12

申请人： Howard Thomas Olnowich ,  Michael Wayland Dotson ,  James William Feeney ,  Michael Hans Fisher ,  John David Jabusch ,  Robert Francis Lusch ,  Michael Anthony Maniguet

发明人： Howard Thomas Olnowich ,  Michael Wayland Dotson ,  James William Feeney ,  Michael Hans Fisher ,  John David Jabusch ,  Robert Francis Lusch ,  Michael Anthony Maniguet

IPC分类号： G06F15/173 ,  H04L7/033 ,  H04L12/18 ,  H04L12/56 ,  H04Q11/00 ,  G06F1/00

CPC分类号： H04L49/153 ,  G06F15/17375 ,  H04L49/256 ,  H04L49/30 ,  H04L49/3081 ,  H04L7/0338 ,  H04L12/1881 ,  H04L2012/5627 ,  H04L49/101 ,  H04L49/1515 ,  H04L49/253 ,  H04L49/555 ,  H04L49/557 ,  H04Q11/0066

摘要： A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus controls the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. The communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.

摘要翻译： 将标准处理器总线协议和架构（如MicroChannel（IBM商标）总线）转换并适应于更渐进的交换机互连协议和架构的转换设备。 现有的基于总线的架构通过启用数千个处理器的互连来扩展到执行并行和集群功能。 转换装置通过使用由智能总线主控器控制的直接存储器访问能力来控制通过交换机网络从一个节点元件到另一个节点元素的数据消息传输。 在消息传输期间，这种方法不需要处理器在节点元素处的交互式支持，并且释放两个处理器来执行其他任务。 通信媒体是基于交换机的并且完全并行，同时支持n个传输，其中n是由交换网络互连的节点的数量。