摘要:
A stereo decoder and a method therefor are provided. The stereo decoder receives a MPX signal from an FM demodulator, and comprises a first auto-calibration circuit, a band-pass filter, a second auto-calibration circuit, a slicer and a PLL circuit. The first auto-calibration circuit generates a first control signal. The band-pass filter generates the pilot signal by filtering the MPX signal with a center frequency set by the first control signal. The second auto-calibration circuit generates a second control signal. The slicer converts the pilot signal into a square wave signal. The PLL circuit comprises a voltage controlled oscillator for generating an oscillation frequency in response to the second control signal. The PLL circuit receives the square wave signal to generate the reference signal around the predetermined frequency in response to the oscillation frequency.
摘要:
A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.
摘要:
A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.
摘要:
A stereo decoder and a method therefor are provided. The stereo decoder receives a MPX signal from an FM demodulator, and comprises a first auto-calibration circuit, a band-pass filter, a second auto-calibration circuit, a slicer and a PLL circuit. The first auto-calibration circuit generates a first control signal. The band-pass filter generates the pilot signal by filtering the MPX signal with a center frequency set by the first control signal. The second auto-calibration circuit generates a second control signal. The slicer converts the pilot signal into a square wave signal. The PLL circuit comprises a voltage controlled oscillator for generating an oscillation frequency in response to the second control signal. The PLL circuit receives the square wave signal to generate the reference signal around the predetermined frequency in response to the oscillation frequency.
摘要:
A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein.
摘要:
A device for processing a radio frequency (RF) signal of an optical disk drive includes a high-pass (HP) filter, an RF variable gain amplifier (VGA), an RF analog-digital converter (ADC), and a digital module. The HP filter filters the RF signal and is capable of selectively utilizing one of a first cut-off frequency and a second cut-off frequency. The RF VGA amplifies the filtered RF signal. The RF ADC converts the amplified RF signal into a digital code. The digital module is capable of executing a first function and a second function with the digital code. The HP filter utilizes the first cut-off frequency when the digital module desires to execute the first function, and the HP filter utilizes the second cut-off frequency when the digital module desires to execute the second function.
摘要:
A processing circuit for optical data is provided. The processing circuit includes a signal-processing module and a radio frequency (RF) signal-summing module. The signal-processing module averages and filters the data signals to obtain a low-frequency signal. The RF signal-summing module receives the data signals and the low-frequency signal, sums the data signals to obtain a summed data signal, and subtracts the low-frequency signal from the summed data signal to obtain a RF summing signal.
摘要:
A liquid-cooled pipe for use in a liquid-cooled heat sink kit is disclosed to include a pipe body, which has a close end, an open end, an axial passage extending from the close end to the open end, and a longitudinal series of through holes in the peripheral wall, a plurality of partition members respectively inserted into the axial passage of the pipe body connected in series with the partition plate of one partition member stopped against the legs of next such that each two adjacent partition members define with the pipe body a respective small chamber in fluid communication with two through holes of the pipe body, and an end cover plate fixedly fastened to the pipe body to seal the open end.
摘要:
A voltage regulator includes a pass transistor, an operational amplifier and a voltage divider circuit. The pass transistor receives a supply voltage to generate a regulated output voltage according to a control signal. The operational amplifier generates the control signal according to a feedback voltage. The voltage divider circuit generates the feedback voltage at a feedback node according to the regulated output voltage, and includes a string of resistors and a stabilization element. The string of resistors is coupled to the pass transistor and includes multiple resistors. The stabilization element is coupled to the resistors and receives the regulated output voltage.
摘要:
An offset calibration method is provided. Two input terminals of an equalizer are switched to a common voltage at a first time point, wherein the equalizer generates a first equalized signal and a second equalized signal according to the common voltage. It is determined whether a first offset voltage is present in the equalizer according to the first and second equalized signals generated from the common voltage. If the first offset voltage is determined to be present in the equalizer, a first compensation voltage is provided to the equalizer.