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1.发明申请ALL-DIGITAL PHASE-LOCKED LOOP, LOOP BANDWIDTH CALIBRATION METHOD, AND LOOP GAIN CALIBRATION METHOD FOR THE SAME 有权全数字锁相环路，环路带宽校准方法及其环路增益校准方法公开(公告)号：US20090096538A1
公开(公告)日：2009-04-16
申请号：US12235615
申请日：2008-09-23
IPC分类号： H03L7/08
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.
摘要翻译： 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。
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2.发明授权All-digital phase-locked loop, loop bandwidth calibration method, and loop gain calibration method for the same 有权全数字锁相环，环路带宽校准方法和环路增益校准方法相同公开(公告)号：US08228128B2
公开(公告)日：2012-07-24
申请号：US12838502
申请日：2010-07-19
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.
摘要翻译： 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。
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3.发明授权All-digital phase-locked loop, loop bandwidth calibration method, and loop gain calibration method for the same 有权全数字锁相环，环路带宽校准方法和环路增益校准方法相同公开(公告)号：US07791428B2
公开(公告)日：2010-09-07
申请号：US12235615
申请日：2008-09-23
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.
摘要翻译： 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。
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4.发明申请ALL-DIGITAL PHASE-LOCKED LOOP, LOOP BANDWIDTH CALIBRATION METHOD, AND LOOP GAIN CALIBRATION METHOD FOR THE SAME 有权全数字锁相环路，环路带宽校准方法及其环路增益校准方法公开(公告)号：US20100277244A1
公开(公告)日：2010-11-04
申请号：US12838502
申请日：2010-07-19
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.
摘要翻译： 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。
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5.发明授权Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof 有权误差保护方法，TDC模块，CTDC模块，全数字锁相环及其校准方法公开(公告)号：US08429487B2
公开(公告)日：2013-04-23
申请号：US12982918
申请日：2010-12-31
IPC分类号： H03M13/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.
摘要翻译： 用于全数字锁相环（ADPLL）的时间 - 数字转换器（TDC）解码器的误差保护方法包括：检索由TDC解码器接收的数字码; 检索由TDC解码器接收的周期代码; 对数字代码的第一预定位执行异或运算，以及循环码的第二预定位用于产生错误保护代码; 并且通过将错误保护代码添加到周期代码中并将循环码移位第三预定位数，并使用错误保护代码来修正周期代码内的错误。
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6.发明申请Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof 有权错误保护方法，TDC模块，CTDC模块，全数字锁相环及其校准方法公开(公告)号：US20090096539A1
公开(公告)日：2009-04-16
申请号：US12235624
申请日：2008-09-23
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.
摘要翻译： 错误预测码被添加到周期信号中，以提高时间数字（TDC）解码器的输出信号的精度。 在全数字锁相环（ADPLL）的相位频率检测器（PFD）/ CTDC模块中专门设计了循环TDC（CTDC），用于增强ADPLL的环路带宽校准。 在PFD / CTDC模块上使用校准方法，以增强ADPLL的环路带宽校准。
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7.发明授权Error compensation method, digital phase error cancellation module, and ADPLL thereof 失效误差补偿方法，数字相位误差消除模块及其ADPLL公开(公告)号：US08395453B2
公开(公告)日：2013-03-12
申请号：US12235623
申请日：2008-09-23
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.
摘要翻译： 通过预测根据估计的量化误差预测的可能的相位误差来补偿全数字锁相环（ADPLL）内的时间 - 数字转换器（TDC）的相位误差，数字控制 振荡器（DCO），TDC的增益或其组合。 通过适当的导入，可能的相位误差可以由量化误差进一步指示，对应于具有TDC的TDC模块接收的参考周期的一半的代码方差，ADPLL的分频器的分频比，分数 与量化误差相关的数字或其组合。 数字相位误差消除模块还用于产生用于补偿TDC的相位误差的可能的相位误差。
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8.发明授权Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof 有权误差保护方法，TDC模块，CTDC模块，全数字锁相环及其校准方法公开(公告)号：US08031007B2
公开(公告)日：2011-10-04
申请号：US12235624
申请日：2008-09-23
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.
摘要翻译： 错误预测码被添加到周期信号中，以提高时间数字（TDC）解码器的输出信号的精度。 在全数字锁相环（ADPLL）的相位频率检测器（PFD）/ CTDC模块中专门设计了循环TDC（CTDC），用于增强ADPLL的环路带宽校准。 在PFD / CTDC模块上使用校准方法，以增强ADPLL的环路带宽校准。
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9.发明申请Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof 有权错误保护方法，TDC模块，CTDC模块，全数字锁相环及其校准方法公开(公告)号：US20110099450A1
公开(公告)日：2011-04-28
申请号：US12982918
申请日：2010-12-31
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.
摘要翻译： 用于全数字锁相环（ADPLL）的时间 - 数字转换器（TDC）解码器的误差保护方法包括：检索由TDC解码器接收的数字码; 检索由TDC解码器接收的周期代码; 对数字代码的第一预定位执行异或运算，以及循环码的第二预定位用于产生错误保护代码; 并且通过将错误保护代码添加到周期代码中并将循环码移位第三预定位数，并使用错误保护代码来修正周期代码内的错误。
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10.发明申请Error Compensation Method, Digital Phase Error Cancellation Module, and ADPLL thereof 失效错误补偿方法，数字相位误差消除模块及其ADPLL公开(公告)号：US20090097609A1
公开(公告)日：2009-04-16
申请号：US12235623
申请日：2008-09-23
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error o a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.
摘要翻译： 通过预测根据估计的量化误差预测的可能的相位误差来补偿全数字锁相环（ADPLL）内的时间 - 数字转换器（TDC）的相位误差，数字控制 振荡器（DCO），TDC的增益或其组合。 通过适当的导入，可能的相位误差可以由量化误差进一步指示，对应于具有TDC的TDC模块接收的参考周期的一半的代码方差，ADPLL的分频器的分频比，分数 与其量化误差的组合相关的数字。 数字相位误差消除模块还用于产生用于补偿TDC的相位误差的可能的相位误差。
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