公开(公告)号：US07494884B2

公开(公告)日：2009-02-24

申请号：US11543435

申请日：2006-10-05

申请人： Hsien-Hsin Lin ,  Li-Te S. Lin ,  Tze-Liang Lee ,  Ming-Hua Yu

发明人： Hsien-Hsin Lin ,  Li-Te S. Lin ,  Tze-Liang Lee ,  Ming-Hua Yu

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/44

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7848

摘要： MOS transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice spacing different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe or SiC. An epitaxy process that includes using HCl gas selectively forms a stressor layer within the crystalline source/drain regions and not on polycrystalline regions of the structure. A preferred epitaxy process dispenses with the source/drain hard mask required of conventional methods. The embedded SiGe stressor applies a compressive strain to a transistor channel region. In another embodiment, the embedded stressor comprises SiC, and it applies a tensile strain to the transistor channel region.

摘要翻译： 提供了具有用于改善载流子迁移率的局部应力源的MOS晶体管。 本发明的实施例包括形成在衬底上的栅极电极，栅电极下的衬底中的载流子通道区域和载流子通道区域两侧的源极/漏极区域。 源极/漏极区域包括具有与衬底不同的晶格间距的嵌入式应力源。 在优选实施例中，衬底是硅，并且嵌入的应力器是SiGe或SiC。 包括使用HCl气体的外延工艺选择性地在结晶源/漏区内形成应力层，而不是在结构的多晶区上形成。 优选的外延工艺省去了常规方法所需的源极/漏极硬掩模。 嵌入式SiGe应力器将压应变应用于晶体管沟道区。 在另一个实施例中，嵌入式应力器包括SiC，并且其对晶体管沟道区域施加拉伸应变。

公开(公告)号：US20080083948A1

公开(公告)日：2008-04-10

申请号：US11543435

申请日：2006-10-05

申请人： Hsien-Hsin Lin ,  Li-Te S. Lin ,  Tze-Liang Lee ,  Ming-Hua Yu

发明人： Hsien-Hsin Lin ,  Li-Te S. Lin ,  Tze-Liang Lee ,  Ming-Hua Yu

IPC分类号： H01L21/8234

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7848

摘要： MOS transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice spacing different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe or SiC. An epitaxy process that includes using HCl gas selectively forms a stressor layer within the crystalline source/drain regions and not on polycrystalline regions of the structure. A preferred epitaxy process dispenses with the source/drain hard mask required of conventional methods. The embedded SiGe stressor applies a compressive strain to a transistor channel region. In another embodiment, the embedded stressor comprises SiC, and it applies a tensile strain to the transistor channel region.

摘要翻译： 提供了具有用于改善载流子迁移率的局部应力源的MOS晶体管。 本发明的实施例包括形成在衬底上的栅极电极，栅电极下的衬底中的载流子通道区域和载流子通道区域两侧的源极/漏极区域。 源极/漏极区域包括具有与衬底不同的晶格间距的嵌入式应力源。 在优选实施例中，衬底是硅，并且嵌入的应力器是SiGe或SiC。 包括使用HCl气体的外延工艺选择性地在结晶源/漏区内形成应力层，而不是在结构的多晶区上形成。 优选的外延工艺省去了常规方法所需的源极/漏极硬掩模。 嵌入式SiGe应力器将压应变应用于晶体管沟道区。 在另一个实施例中，嵌入式应力器包括SiC，并且其对晶体管沟道区域施加拉伸应变。

公开(公告)号：US20110230022A1

公开(公告)日：2011-09-22

申请号：US13117782

申请日：2011-05-27

申请人： Ming-Hua Yu ,  Ling-Yen Yeh ,  Tze-Liang Lee

发明人： Ming-Hua Yu ,  Ling-Yen Yeh ,  Tze-Liang Lee

IPC分类号： H01L21/8238 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.

摘要翻译： 一种半导体器件及其制造方法，其中所述衬底内的晶体管的PMOS源极/漏极区域包括所述PMOS源极/漏极区域中的第一应变层和与所述第一应变层接触的第一覆盖层。 此外，半导体器件和方法提供了衬底内的晶体管的NMOS源极/漏极区域，其包括NMOS源极/漏极区域中的第二应变层和与第二应变层接触的第二覆盖层。

公开(公告)号：US07973337B2

公开(公告)日：2011-07-05

申请号：US12844896

申请日：2010-07-28

申请人： Ming-Hua Yu ,  Ling-Yen Yeh ,  Tze-Liang Lee

发明人： Ming-Hua Yu ,  Ling-Yen Yeh ,  Tze-Liang Lee

IPC分类号： H01L31/0328

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.

摘要翻译： 一种半导体器件及其制造方法，其中所述衬底内的晶体管的PMOS源极/漏极区域包括所述PMOS源极/漏极区域中的第一应变层和与所述第一应变层接触的第一覆盖层。 此外，半导体器件和方法提供了衬底内的晶体管的NMOS源极/漏极区域，其包括NMOS源极/漏极区域中的第二应变层和与第二应变层接触的第二覆盖层。

公开(公告)号：US20110049567A1

公开(公告)日：2011-03-03

申请号：US12841763

申请日：2010-07-22

申请人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

发明人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66636

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.

摘要翻译： 本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域 在硅衬底中，对硅衬底中的凹部进行无偏压蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中形成半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。 因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

公开(公告)号：US07781799B2

公开(公告)日：2010-08-24

申请号：US11923420

申请日：2007-10-24

申请人： Ming-Hua Yu ,  Ling-Yen Yeh ,  Tze-Liang Lee

发明人： Ming-Hua Yu ,  Ling-Yen Yeh ,  Tze-Liang Lee

IPC分类号： H01L31/0328

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.

摘要翻译： 一种半导体器件及其制造方法，其中所述衬底内的晶体管的PMOS源极/漏极区域包括所述PMOS源极/漏极区域中的第一应变层和与所述第一应变层接触的第一覆盖层。 此外，半导体器件和方法提供了衬底内的晶体管的NMOS源极/漏极区域，其包括NMOS源极/漏极区域中的第二应变层和与第二应变层接触的第二覆盖层。

公开(公告)号：US09054130B2

公开(公告)日：2015-06-09

申请号：US12841763

申请日：2010-07-22

申请人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

发明人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

IPC分类号： H01L21/302 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66636

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.

摘要翻译： 本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域 在硅衬底中，对硅衬底中的凹陷区域进行非偏置蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中生长半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。 因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

公开(公告)号：US08530316B2

公开(公告)日：2013-09-10

申请号：US13736453

申请日：2013-01-08

申请人： Yu-Hung Cheng ,  Jhi-Cherng Lu ,  Ming-Hua Yu ,  Chii-Horng Li ,  Tze-Liang Lee

发明人： Yu-Hung Cheng ,  Jhi-Cherng Lu ,  Ming-Hua Yu ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/20 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66477 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底的表面上生长包括第一半导体材料的第一半导体结构，其中生长第一半导体结构包括在第二半导体结构的第二半导体结构上形成包含第一半导体材料的半导体粒子 半导体器件。 该方法还包括在第一半导体结构上形成第二半导体材料的保护层，其中形成保护层包括在半导体颗粒上形成保护层。 该方法还包括去除保护层的一部分，其中去除保护层的部分包括完全去除半导体颗粒和半导体颗粒上的保护层。

公开(公告)号：US20100289086A1

公开(公告)日：2010-11-18

申请号：US12844896

申请日：2010-07-28

申请人： Ming-Hua Yu ,  Ling-Yen Yeh ,  Tze-Liang Lee

发明人： Ming-Hua Yu ,  Ling-Yen Yeh ,  Tze-Liang Lee

IPC分类号： H01L27/092

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.

摘要翻译： 一种半导体器件及其制造方法，其中所述衬底内的晶体管的PMOS源极/漏极区域包括所述PMOS源极/漏极区域中的第一应变层和与所述第一应变层接触的第一覆盖层。 此外，半导体器件和方法提供了衬底内的晶体管的NMOS源极/漏极区域，其包括NMOS源极/漏极区域中的第二应变层和与第二应变层接触的第二覆盖层。

公开(公告)号：US20070298593A1

公开(公告)日：2007-12-27

申请号：US11521667

申请日：2006-09-15

申请人： Ming-Hua Yu ,  Tze-Liang Lee ,  Pang-Yen Tsai

发明人： Ming-Hua Yu ,  Tze-Liang Lee ,  Pang-Yen Tsai

IPC分类号： H01L21/20 ,  H01L21/84 ,  H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7846

摘要： Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.

摘要翻译： 提供了SOI衬底中具有STI区域的半导体器件的方法和结构。 半导体结构包括在衬底上形成的SOI外延岛。 该结构还包括围绕SOI岛的STI结构。 STI结构包括在衬底上的第二外延层和在第二外延层上的第二电介质层。 一种半导体制造方法包括在衬底上形成介电层并围绕延伸穿过介电层的隔离沟槽围绕衬底中的器件制造区域。 该方法还包括用第一外延层填充隔离沟槽，并在器件制造区域上方和第一外延层上形成第二外延层。 然后用绝缘电介质代替第一外延层的一部分，然后在器件制造区域内形成诸如晶体管的器件的第二外延层。