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公开(公告)号:US20110049567A1
公开(公告)日:2011-03-03
申请号:US12841763
申请日:2010-07-22
Applicant: Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
Inventor: Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7848 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66636
Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.
Abstract translation: 本公开提供了一种制造半导体器件的方法,其包括提供硅衬底,在硅衬底上形成栅极堆叠,对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分,从而形成凹陷区域 在硅衬底中,对硅衬底中的凹部进行无偏压蚀刻工艺,从而在硅衬底中形成瓶颈形凹部区域,并且在瓶颈形凹部区域中形成半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺,包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺,并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅,来对硅衬底中的凹陷区域进行氧化处理。 因此,这些方法形成聚合物保护以帮助形成瓶颈形凹部。
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公开(公告)号:US20060196417A1
公开(公告)日:2006-09-07
申请号:US11070149
申请日:2005-03-03
Applicant: Chia-Hui Lin , Shih-Hao Lo , Tsang-Yu Liu , Szu-An Wu , Cheng-Hui Yang , Yi-Fang Lai , Chien Lin
Inventor: Chia-Hui Lin , Shih-Hao Lo , Tsang-Yu Liu , Szu-An Wu , Cheng-Hui Yang , Yi-Fang Lai , Chien Lin
IPC: C23C16/00
CPC classification number: C23C16/45574 , C23C16/4558
Abstract: Gas distribution systems for deposition processes and methods of using the same. A substrate support member holding a substrate is disposed in a processing chamber. A plurality of first and second gas nozzles is connected to a gas distribution ring disposed in the processing chamber. The first gas nozzles provide a first reactant gas and include at least first and second outlet apertures. The second gas nozzles provide a second reactant gas and include third outlet apertures. The first outlet aperture is larger than the second outlet aperture, such that the first gas nozzle with the first outlet aperture creates an increased gas flow adjacent to a determined portion of the substrate to increase deposition from the first reactant gas on the determined portion of the substrate.
Abstract translation: 用于沉积工艺的气体分配系统及其使用方法。 保持基板的基板支撑构件设置在处理室中。 多个第一和第二气体喷嘴连接到设置在处理室中的气体分配环。 第一气体喷嘴提供第一反应气体并且包括至少第一和第二出口孔。 第二气体喷嘴提供第二反应气体并且包括第三出口孔。 第一出口孔大于第二出口孔,使得具有第一出口孔的第一气体喷嘴产生与衬底的确定部分相邻的增加的气流,以增加第一反应气体在所确定的部分上的沉积 基质。
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公开(公告)号:US09054130B2
公开(公告)日:2015-06-09
申请号:US12841763
申请日:2010-07-22
Applicant: Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
Inventor: Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
IPC: H01L21/302 , H01L29/66 , H01L21/306 , H01L21/3065 , H01L29/165
CPC classification number: H01L29/7848 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66636
Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.
Abstract translation: 本公开提供了一种制造半导体器件的方法,其包括提供硅衬底,在硅衬底上形成栅极堆叠,对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分,从而形成凹陷区域 在硅衬底中,对硅衬底中的凹陷区域进行非偏置蚀刻工艺,从而在硅衬底中形成瓶颈形凹部区域,并且在瓶颈形凹部区域中生长半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺,包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺,并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅,来对硅衬底中的凹陷区域进行氧化处理。 因此,这些方法形成聚合物保护以帮助形成瓶颈形凹部。
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4.
公开(公告)号:US20130056837A1
公开(公告)日:2013-03-07
申请号:US13244365
申请日:2011-09-24
Applicant: Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
Inventor: Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC: H01L29/772 , H01L21/336 , H01L21/28
CPC classification number: H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
Abstract translation: 制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。 在半导体衬底上形成金属栅极结构,并在其上形成一个薄的电介质膜。 薄介电膜包括从金属栅极与金属组合的氮氧化合物。 该方法还包括在金属栅极结构的两侧提供层间电介质(ILD)。
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5.
公开(公告)号:US08822283B2
公开(公告)日:2014-09-02
申请号:US13244365
申请日:2011-09-24
Applicant: Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
Inventor: Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC: H01L21/336 , H01L21/8234 , H01L29/66
CPC classification number: H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
Abstract translation: 制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。 在半导体衬底上形成金属栅极结构,并在其上形成一个薄的电介质膜。 薄介电膜包括从金属栅极与金属组合的氮氧化合物。 该方法还包括在金属栅极结构的两侧提供层间电介质(ILD)。
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