公开(公告)号：US06858516B2

公开(公告)日：2005-02-22

申请号：US10279511

申请日：2002-10-23

申请人： Tzu-En Ho ,  Chang Rong Wu ,  Hsin-Jung Ho

发明人： Tzu-En Ho ,  Chang Rong Wu ,  Hsin-Jung Ho

IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.

摘要翻译： 高宽比浅沟槽隔离区域的制造方法。 提供其中具有沟槽的衬底并将其放置在室中。 第一绝缘层通过高密度等离子体化学气相沉积形成在衬底上以及沟内。 通过使用氟化碳作为蚀刻气体的原位蚀刻除去沟槽外部的第一绝缘层的大部分，对SiO 2 / SiN蚀刻比率具有高选择性，并且通过高密度等离子体化学品在第一绝缘层上形成第二绝缘层 气相沉积，填充沟槽。 根据本发明，可以实现无空隙的高纵横比浅沟槽隔离区域。

公开(公告)号：US06833311B2

公开(公告)日：2004-12-21

申请号：US10426327

申请日：2003-04-30

申请人： Hsin-Jung Ho ,  Chang Rong Wu ,  Tzu En Ho

发明人： Hsin-Jung Ho ,  Chang Rong Wu ,  Tzu En Ho

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

公开(公告)号：US06828239B2

公开(公告)日：2004-12-07

申请号：US10121504

申请日：2002-04-11

申请人： Tzu En-Ho ,  Chang Rong Wu ,  Hsin-Jung Ho

发明人： Tzu En-Ho ,  Chang Rong Wu ,  Hsin-Jung Ho

IPC分类号： H01L21301

CPC分类号： H01L21/76224

摘要： A method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate. The method includes the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.

摘要翻译： 一种在半导体衬底中形成高纵横比浅沟槽隔离的方法。 该方法包括以下步骤：在半导体衬底上形成具有一定图案的硬掩模层，蚀刻未被硬掩模层覆盖的半导体衬底的一部分，以在半导体衬底中形成高纵横比的浅沟槽; 在高纵横比浅沟槽的底部和侧壁上形成氧化物衬垫; 执行LPCVD以形成第一氧化物层以填充高纵横比浅沟槽，在第一氧化物层中形成空隙; 将所述第一氧化物层的一部分蚀刻到所述高纵横比浅沟槽的一定深度并暴露所述空隙; 并且执行HDPCVD以形成第二氧化物层以填充高纵横比浅沟槽。

公开(公告)号：US08395139B1

公开(公告)日：2013-03-12

申请号：US13311576

申请日：2011-12-06

申请人： Hsin-Jung Ho ,  Chang-Rong Wu ,  Wei-Chia Chen

发明人： Hsin-Jung Ho ,  Chang-Rong Wu ,  Wei-Chia Chen

IPC分类号： H01L47/00

CPC分类号： H01L27/2454 ,  H01L45/146 ,  H01L45/1683

摘要： A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.

摘要翻译： 存储器结构包括由第一隔离沟槽和第二隔离沟槽包围的有源区域; 凹陷到半导体衬底的有源区域中的位线沟槽; 凹入到半导体衬底的有源区域中且比位线沟槽浅的字线沟槽。 位线沟槽和字线沟槽将有源区域分成四个柱状子区域。 位线被嵌入位线沟槽中。 字线嵌入字线沟槽中。 每个柱状子区域内置有一个垂直晶体管。 电阻式存储器元件电耦合到垂直晶体管。

公开(公告)号：US06693006B2

公开(公告)日：2004-02-17

申请号：US10322111

申请日：2002-12-17

申请人： Hsin-Jung Ho ,  Chang Rong Wu ,  Yi-Nan Chen ,  Tung-Wang Huang

发明人： Hsin-Jung Ho ,  Chang Rong Wu ,  Yi-Nan Chen ,  Tung-Wang Huang

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L21/3086 ,  H01L29/66181 ,  H01L29/945

摘要： A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.

摘要翻译： 一种增加沟槽电容器面积的方法。 首先，在基板上依次形成第一氧化物层和第一氮化物层。 通过第一氧化物层和第一氮化物层形成到衬底中的开口。 去除暴露在开口中的第一氧化物层的一部分以形成第一凹部，然后在其中形成第二氮化物层。 第二氧化物层形成在开口的下部。 在开口的上部形成第三氮化物层后，除去第二氧化物层。 使用第一氮化物层，第二氮化物层和第三氮化物层作为掩模来蚀刻开口中的衬底，以在开口的下部形成第二凹部。 然后去除第二氮化物层和第三氮化物层。

公开(公告)号：US07232718B2

公开(公告)日：2007-06-19

申请号：US10605234

申请日：2003-09-17

申请人： Chih-Han Chang ,  Hsin-Jung Ho ,  Chang-Rong Wu ,  Chien-Jung Sun

发明人： Chih-Han Chang ,  Hsin-Jung Ho ,  Chang-Rong Wu ,  Chien-Jung Sun

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087

摘要： A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited in the deep trench, and etched back to expose parts of the doped silicate film. Then, an etching process is performed to remove the exposed doped silicate film and parts of the pad oxide for forming a recess. The sacrificial layer is removed. A silicon nitride layer is deposited to fill the recess and to cover the doped silicate film. Finally, a thermal oxidation process is performed to form a doped ion region. The silicon nitride layer is removed. The doped silicate film is removed.

摘要翻译： 一种形成深沟槽电容器掩埋板的方法。 提供具有衬垫氧化物和衬垫氮化物的衬底。 在衬底中形成深沟槽。 掺杂的硅酸盐膜沉积在深沟槽的侧壁上。 牺牲层沉积在深沟槽中，并被回蚀以暴露部分掺杂的硅酸盐膜。 然后，进行蚀刻处理以去除暴露的掺杂硅酸盐膜和用于形成凹槽的衬垫氧化物的一部分。 牺牲层被去除。 沉积氮化硅层以填充凹部并覆盖掺杂的硅酸盐膜。 最后，进行热氧化工艺以形成掺杂的离子区域。 去除氮化硅层。 去除掺杂的硅酸盐膜。

公开(公告)号：US06770563B2

公开(公告)日：2004-08-03

申请号：US10336083

申请日：2003-01-03

申请人： Tung-Wang Huang ,  Chang Rong Wu ,  Chien-Mao Liao ,  Hsin-Jung Ho

发明人： Tung-Wang Huang ,  Chang Rong Wu ,  Chien-Mao Liao ,  Hsin-Jung Ho

IPC分类号： H01L21311

CPC分类号： H01L27/1087 ,  H01L21/3083 ,  H01L29/66181

摘要： A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.

摘要翻译： 形成瓶状沟槽的工艺。 提供具有沟槽的半导体衬底，其上依次形成衬垫层和硬掩模层。 在硬掩模层上形成电介质层以填充沟槽。 蚀刻介电层的一部分以暴露沟槽上部的侧壁。 在侧壁上形成间隔物。 去除沟槽中的残余介电层，并且不被间隔物覆盖的部分沟槽被蚀刻成瓶形。

公开(公告)号：US20130075812A1

公开(公告)日：2013-03-28

申请号：US13239389

申请日：2011-09-22

申请人： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

发明人： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

IPC分类号： H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

摘要翻译： 单面存取装置包括活动鳍片结构，其包括源极接触区域和通过它们之间的隔离区域彼此分离的漏极接触区域; 沟槽隔离结构，设置在所述有源鳍结构的一侧，其中所述沟槽隔离结构与所述源极接触区域和所述漏极接触区域之间的隔离区域相交; 侧壁门，其设置在所述隔离区域下方并且在所述有源鳍结构的另一侧与所述沟槽隔离结构相对，使得所述有源鳍结构被所述沟槽隔离结构和所述侧壁栅极夹持，其中所述侧壁门具有多指 与活跃的鳍结构互动; 以及在侧壁浇口和活性鳍结构之间的栅介质层。

公开(公告)号：US08395209B1

公开(公告)日：2013-03-12

申请号：US13239389

申请日：2011-09-22

申请人： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

发明人： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

IPC分类号： H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

摘要翻译： 单面存取装置包括活动鳍片结构，其包括源极接触区域和通过它们之间的隔离区域彼此分离的漏极接触区域; 沟槽隔离结构，设置在所述有源鳍结构的一侧，其中所述沟槽隔离结构与所述源极接触区域和所述漏极接触区域之间的隔离区域相交; 侧壁门，其设置在所述隔离区域下方并且在所述有源鳍结构的另一侧与所述沟槽隔离结构相对，使得所述有源鳍结构被所述沟槽隔离结构和所述侧壁栅极夹持，其中所述侧壁门具有多指 与活跃的鳍结构互动; 以及在侧壁浇口和活性鳍结构之间的栅介质层。

公开(公告)号：US20050059207A1

公开(公告)日：2005-03-17

申请号：US10605234

申请日：2003-09-17

申请人： Chih-Han Chang ,  Hsin-Jung Ho ,  Chang-Rong Wu ,  Chien-Jung Sun

发明人： Chih-Han Chang ,  Hsin-Jung Ho ,  Chang-Rong Wu ,  Chien-Jung Sun

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/1087

摘要： A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited in the deep trench, and etched back to expose parts of the doped silicate film. Then, an etching process is performed to remove the exposed doped silicate film and parts of the pad oxide for forming a recess. The sacrificial layer is removed. A silicon nitride layer is deposited to fill the recess and to cover the doped silicate film. Finally, a thermal oxidation process is performed to form a doped ion region. The silicon nitride layer is removed. The doped silicate film is removed.

摘要翻译： 一种形成深沟槽电容器掩埋板的方法。 提供具有衬垫氧化物和衬垫氮化物的衬底。 在衬底中形成深沟槽。 掺杂的硅酸盐膜沉积在深沟槽的侧壁上。 牺牲层沉积在深沟槽中，并被回蚀以暴露部分掺杂的硅酸盐膜。 然后，进行蚀刻处理以去除暴露的掺杂硅酸盐膜和用于形成凹槽的衬垫氧化物的一部分。 牺牲层被去除。 沉积氮化硅层以填充凹部并覆盖掺杂的硅酸盐膜。 最后，进行热氧化工艺以形成掺杂的离子区域。 去除氮化硅层。 去除掺杂的硅酸盐膜。