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    Manufacturing method of a high aspect ratio shallow trench isolation region
    1.
    发明授权
    Manufacturing method of a high aspect ratio shallow trench isolation region 有权
    高深宽比浅沟槽隔离区的制造方法

    公开(公告)号：US06858516B2

    公开(公告)日：2005-02-22

    申请号：US10279511

    申请日：2002-10-23

    申请人： Tzu-En Ho ,  Chang Rong Wu ,  Hsin-Jung Ho

    发明人： Tzu-En Ho ,  Chang Rong Wu ,  Hsin-Jung Ho

    IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L21/76

    CPC分类号： H01L21/76224

    摘要： A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.

    摘要翻译： 高宽比浅沟槽隔离区域的制造方法。 提供其中具有沟槽的衬底并将其放置在室中。 第一绝缘层通过高密度等离子体化学气相沉积形成在衬底上以及沟内。 通过使用氟化碳作为蚀刻气体的原位蚀刻除去沟槽外部的第一绝缘层的大部分，对SiO 2 / SiN蚀刻比率具有高选择性，并且通过高密度等离子体化学品在第一绝缘层上形成第二绝缘层 气相沉积，填充沟槽。 根据本发明，可以实现无空隙的高纵横比浅沟槽隔离区域。

    Method for fabricating semiconductor device having stacked-gate structure
    2.
    发明授权
    Method for fabricating semiconductor device having stacked-gate structure 有权
    具有层叠栅结构的半导体器件的制造方法

    公开(公告)号：US07375017B2

    公开(公告)日：2008-05-20

    申请号：US11338579

    申请日：2006-01-23

    申请人： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

    发明人： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28052 ,  H01L29/4933

    摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

    摘要翻译： 一种半导体制造方法，该半导体器件具有堆叠栅极结构。 通过介电层与衬底绝缘的衬底上形成多晶硅层。 在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。 使用氮气和氢气对氮化钨层进行退火。 依次形成覆盖氮化钨层的钨层和覆盖层。

    Method of fabricating a shallow trench isolation structure
    4.
    发明授权
    Method of fabricating a shallow trench isolation structure 有权
    制造浅沟槽隔离结构的方法

    公开(公告)号：US06737334B2

    公开(公告)日：2004-05-18

    申请号：US10268522

    申请日：2002-10-09

    申请人： Tzu-En Ho ,  Chang Rong Wu ,  Yi-Nan Chen

    发明人： Tzu-En Ho ,  Chang Rong Wu ,  Yi-Nan Chen

    IPC分类号： H01L218242

    CPC分类号： H01L21/76224 ,  H01L21/31111

    摘要： A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.

    摘要翻译： 一种制造用于半导体器件的STI的方法。 该方法包括以下步骤。 在半导体衬底上形成沟槽，在沟槽的底部和侧壁上形成衬里氧化物，然后在衬里氧化物上形成衬里氮化物。 第一氧化物层通过高密度等离子体化学气相沉积沉积在沟槽中。 将第一氧化物层喷雾刻蚀至预定深度，其中喷雾蚀刻溶液的配方为HF / H 2 SO 4 = 0.3〜0.4。 沉积第二氧化物层以通过高密度等离子体化学气相沉积填充沟槽以形成浅沟槽隔离结构。

    Method for fabricating semiconductor device having stacked-gate structure
    5.
    发明授权
    Method for fabricating semiconductor device having stacked-gate structure 有权
    具有层叠栅结构的半导体器件的制造方法

    公开(公告)号：US07022603B2

    公开(公告)日：2006-04-04

    申请号：US10683612

    申请日：2003-10-10

    申请人： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

    发明人： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28052 ,  H01L29/4933

    摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

    摘要翻译： 一种半导体制造方法，该半导体器件具有堆叠栅极结构。 通过介电层与衬底绝缘的衬底上形成多晶硅层。 在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。 使用氮气和氢气对氮化钨层进行退火。 依次形成覆盖氮化钨层的钨层和覆盖层。

    Methods for manufacturing stacked gate structure and field effect transistor povided with the same
    7.
    发明申请
    Methods for manufacturing stacked gate structure and field effect transistor povided with the same 有权
    堆叠栅极结构和场效应晶体管的制造方法相同

    公开(公告)号：US20050074957A1

    公开(公告)日：2005-04-07

    申请号：US10864320

    申请日：2004-06-10

    申请人： Tzu-En Ho ,  Chang-Rong Wu

    发明人： Tzu-En Ho ,  Chang-Rong Wu

    IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/7833 ,  H01L21/28061 ,  H01L29/4933

    摘要： The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

    摘要翻译： 本发明提供一种在半导体器件中制造堆叠栅极结构的方法。 该方法包括以下步骤：在半导体衬底上依次形成栅介质层，多晶硅层，钛层和WNX层，在氮气环境中进行快速热退火（RTA），形成氮化硅 层，并且将多层薄膜结构图案化成预定的构造。

    Methods for manufacturing stacked gate structure and field effect transistor provided with the same
    8.
    发明授权
    Methods for manufacturing stacked gate structure and field effect transistor provided with the same 有权
    制造堆叠栅极结构的方法和具有该栅极结构的场效应晶体管

    公开(公告)号：US07101777B2

    公开(公告)日：2006-09-05

    申请号：US10864320

    申请日：2004-06-10

    申请人： Tzu-En Ho ,  Chang-Rong Wu

    发明人： Tzu-En Ho ,  Chang-Rong Wu

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/7833 ,  H01L21/28061 ,  H01L29/4933

    摘要： The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

    摘要翻译： 本发明提供一种在半导体器件中制造堆叠栅极结构的方法。 该方法包括以下步骤：在半导体衬底上顺序地形成栅介质层，多晶硅层，钛层和WN层，并进行快速热退火（RTA） 氮气环境，在钨层上形成氮化硅层，并将多层薄膜结构图案化成预定的构型。