公开(公告)号：US20130075812A1

公开(公告)日：2013-03-28

申请号：US13239389

申请日：2011-09-22

申请人： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

发明人： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

IPC分类号： H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

摘要翻译： 单面存取装置包括活动鳍片结构，其包括源极接触区域和通过它们之间的隔离区域彼此分离的漏极接触区域; 沟槽隔离结构，设置在所述有源鳍结构的一侧，其中所述沟槽隔离结构与所述源极接触区域和所述漏极接触区域之间的隔离区域相交; 侧壁门，其设置在所述隔离区域下方并且在所述有源鳍结构的另一侧与所述沟槽隔离结构相对，使得所述有源鳍结构被所述沟槽隔离结构和所述侧壁栅极夹持，其中所述侧壁门具有多指 与活跃的鳍结构互动; 以及在侧壁浇口和活性鳍结构之间的栅介质层。

公开(公告)号：US08395209B1

公开(公告)日：2013-03-12

申请号：US13239389

申请日：2011-09-22

申请人： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

发明人： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

IPC分类号： H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

摘要翻译： 单面存取装置包括活动鳍片结构，其包括源极接触区域和通过它们之间的隔离区域彼此分离的漏极接触区域; 沟槽隔离结构，设置在所述有源鳍结构的一侧，其中所述沟槽隔离结构与所述源极接触区域和所述漏极接触区域之间的隔离区域相交; 侧壁门，其设置在所述隔离区域下方并且在所述有源鳍结构的另一侧与所述沟槽隔离结构相对，使得所述有源鳍结构被所述沟槽隔离结构和所述侧壁栅极夹持，其中所述侧壁门具有多指 与活跃的鳍结构互动; 以及在侧壁浇口和活性鳍结构之间的栅介质层。

公开(公告)号：US07759190B2

公开(公告)日：2010-07-20

申请号：US11925363

申请日：2007-10-26

申请人： Neng-Tai Shih ,  Jeng-Ping Lin

发明人： Neng-Tai Shih ,  Jeng-Ping Lin

IPC分类号： H01L27/108

CPC分类号： H01L27/10867

摘要： A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on the substrate and neighboring the trench. An opening is formed on the substrate between the collar dielectric layer and the gate structure. Next, a portion of the top dielectric layer and the collar dielectric layer is removed to expose a portion of the conductive column. An insulating layer is deposited on the gate structure and the exposed conductive column, filling the opening. The insulating layer is etched to expose a portion of the capacitor-side region of the substrate and the conductive column. A transmissive strap is formed by selective deposition, electrically connecting the capacitor-side region of the substrate and the conductive column.

摘要翻译： 公开了一种存储器件的制造方法。 提供具有沟槽的衬底，其中包括沟槽电容器，导电柱，套环电介质层和顶部电介质层。 具有侧壁上的间隔物的栅极结构设置在衬底上并与沟槽相邻。 在轴环电介质层和栅极结构之间的基板上形成开口。 接下来，去除顶部电介质层和套环电介质层的一部分以暴露导电柱的一部分。 绝缘层沉积在栅极结构和暴露的导电柱上，填充开口。 蚀刻绝缘层以暴露基板和导电柱的电容器侧区域的一部分。 通过选择性沉积形成透射带，电连接基板的电容器侧区域和导电柱。

公开(公告)号：US20080251829A1

公开(公告)日：2008-10-16

申请号：US11925363

申请日：2007-10-26

申请人： Neng-Tai Shih ,  Jeng-Ping Lin

发明人： Neng-Tai Shih ,  Jeng-Ping Lin

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10867

摘要： A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on the substrate and neighboring the trench. An opening is formed on the substrate between the collar dielectric layer and the gate structure. Next, a portion of the top dielectric layer and the collar dielectric layer is removed to expose a portion of the conductive column. An insulating layer is deposited on the gate structure and the exposed conductive column, filling the opening. The insulating layer is etched to expose a portion of the capacitor-side region of the substrate and the conductive column. A transmissive strap is formed by selective deposition, electrically connecting the capacitor-side region of the substrate and the conductive column.

摘要翻译： 公开了一种存储器件的制造方法。 提供具有沟槽的衬底，其中包括沟槽电容器，导电柱，套环电介质层和顶部电介质层。 具有侧壁上的间隔物的栅极结构设置在衬底上并与沟槽相邻。 在轴环电介质层和栅极结构之间的基板上形成开口。 接下来，去除顶部电介质层和套环电介质层的一部分以暴露导电柱的一部分。 绝缘层沉积在栅极结构和暴露的导电柱上，填充开口。 蚀刻绝缘层以暴露基板和导电柱的电容器侧区域的一部分。 通过选择性沉积形成透射带，电连接基板的电容器侧区域和导电柱。

公开(公告)号：US20050012131A1

公开(公告)日：2005-01-20

申请号：US10604344

申请日：2003-07-14

申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US20140070359A1

公开(公告)日：2014-03-13

申请号：US13615526

申请日：2012-09-13

申请人： Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

发明人： Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

IPC分类号： H01L27/00

CPC分类号： H01L21/3081 ,  H01L21/76224

摘要： A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.

摘要翻译： 存储器阵列包括由第一和第二STI结构围绕的菱形形状的AA区域。 第一STI结构在菱形AA区域的长边上沿着第一方向延伸并且具有深度d1。 第二STI结构沿着菱形AA区域的较短边沿第二方向延伸，并且具有两个深度：d2和d3，其中d1和d2比d3浅。

公开(公告)号：US07541244B2

公开(公告)日：2009-06-02

申请号：US11491704

申请日：2006-07-24

申请人： Jeng-Ping Lin ,  Pei-Ing Lee

发明人： Jeng-Ping Lin ,  Pei-Ing Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7834 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

公开(公告)号：US07285377B2

公开(公告)日：2007-10-23

申请号：US10715616

申请日：2003-11-18

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： G03F7/00

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US06794250B2

公开(公告)日：2004-09-21

申请号：US10449296

申请日：2003-05-29

申请人： Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

发明人： Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

IPC分类号： H01L218247

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

摘要： A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gaze. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.

摘要翻译： 垂直分闸门闪存单元。 存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。 浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。 控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。 栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制注视的绝缘。 第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与控制栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。

公开(公告)号：US06781181B2

公开(公告)日：2004-08-24

申请号：US10453502

申请日：2003-06-04

申请人： Kuen-Chy Heo ,  Jeng-Ping Lin

发明人： Kuen-Chy Heo ,  Jeng-Ping Lin

IPC分类号： H01L27108

CPC分类号： H01L29/945 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10882

摘要： A DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor is disposed in a substrate; a gate is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and an upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. The DRAM cell can be applied to an open bitline DRAM, a folded bitline DRAM, and a folded bitline DRAM with bordless bitline contact window.

摘要翻译： 具有垂直晶体管和深沟槽电容器的DRAM单元。 在DRAM单元中，深沟槽电容器设置在基板中; 栅极设置在深沟槽电容器上; 离子掺杂层设置在电容器的栅极和上电极之间; 绝缘层设置在栅极和离子掺杂层之间; 栅极绝缘层设置在栅极的侧壁上; 沟道区位于衬底的栅极绝缘层的旁边; 源极设置在离子掺杂层的侧壁上并在垂直沟道区的一侧上; 并且在垂直沟道区域的另一侧设置有公共漏极。 DRAM单元可以应用于开放的位线DRAM，折叠位线DRAM和具有无边位线接触窗口的折叠位线DRAM。