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1.发明授权Memory and circuit for accessing data bits in a memory array in multi-data rate operation 有权用于以多数据速率操作访问存储器阵列中的数据位的存储器和电路
公开(公告)号：US6097640A
公开(公告)日：2000-08-01
申请号：US195743
申请日：1998-11-18
CPC分类号： G11C7/1006 , G11C7/1048
摘要： A method and circuit for accessing data bits in a memory array in a multi-data rate operation. In one architecture, a memory device includes a memory array for storing data values, multiple (N) sensing circuits, multiple (K) control lines, and an I/O pad. One sensing circuit couples to each data value being retrieved from the memory device. The I/O pad operatively couples to the sensing circuits. And each control line couples to at least one sensing circuit and has a clock phase unique from remaining control lines.
摘要翻译： 一种用于以多数据速率操作访问存储器阵列中的数据位的方法和电路。 在一种架构中，存储器件包括用于存储数据值的存储器阵列，多个（N）个感测电路，多个（K）控制线和I / O焊盘。 一个感测电路耦合到从存储器件检索的每个数据值。 I / O焊盘可操作地耦合到感测电路。 并且每个控制线耦合到至少一个感测电路，并且具有从剩余控制线唯一的时钟相位。
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2.发明授权
公开(公告)号：US6061292A
公开(公告)日：2000-05-09
申请号：US195268
申请日：1998-11-18
CPC分类号： G11C7/1066 , G11C7/22 , G11C8/10
摘要： Methods and circuits for triggering column select line for write operations in a multiple data rate (e.g., a double data rate) operation. A memory device includes a memory array that stores data values, an address logic circuit that generates an address for the memory array, and a column decoder. The column decoder couples to the address logic circuit and the memory array. The column decoder receives either a data strobe input signal (DQS) or a clock signal (CLK), or both, and activates a column select line for the memory array in response to one of the input signal(s).
摘要翻译： 用于以多数据速率（例如，双数据速率）操作来触发用于写入操作的列选择线的方法和电路。 存储器件包括存储数据值的存储器阵列，产生存储器阵列的地址的地址逻辑电路和列解码器。 列解码器耦合到地址逻辑电路和存储器阵列。 列解码器接收数据选通输入信号（DQS）或时钟信号（CLK）或两者，并且响应于输入信号中的一个激活存储器阵列的列选择线。
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公开(公告)号：US06452843B1
公开(公告)日：2002-09-17
申请号：US09740702
申请日：2000-12-19
IPC分类号： G11C700
摘要： Techniques and circuits for testing high-speed circuits using slow-speed input signals. Various designs for a “stimulus” generator are provided, which is capable of generating a high-speed stimulus based on, or in response to, one or more input signals. In one design, the generator includes two edge detectors coupled to a latch. Each edge detector receives a respective set of input signals and provides an intermediate signal. The latch receives the two intermediate signals from the two edge detectors and generates the output signal, which has a particular waveform pattern generated based on the active (e.g., leading) transitions in the two sets of input signals provided to the two edge detectors. In another design, the generator includes a ring oscillator that is enabled by one input signal, and further initiated by a pulse on another input signal provided to an input of a latch used to implement the oscillator.
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公开(公告)号：US6144610A
公开(公告)日：2000-11-07
申请号：US294512
申请日：1999-04-20
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C11/4085 , G11C8/08
摘要： A memory device that includes a row decoder, a set of word line, and one or more word line pull-down drivers. The row decoder includes decoding circuitry and a set of word line drivers. The decoding circuitry is configured to receive address information and generate a set of word line control signals. The word line drivers couple to the decoding circuitry and are responsive to the word line control signals. Each word line driver is configured to provide pull-up drive capability, and can further be configured to provide pull-down drive capability. Each word line couples to at least one word line driver. The word line pull-down driver(s) couples to the word lines, with each word line pull-down driver being configured to provide pull-down drive capability. One or more word line pull-down drivers can be distributed (i.e., uniformly) along the length of each word line. The word lines can also be implemented using a hierarchical word line architecture that includes a set of main word lines (i.e., fabricated on a metal layer) and a set of segmented word lines (i.e., fabricated on a polysilicon layer) coupled to each main word line.
摘要翻译： 一种包括行解码器，一组字线以及一个或多个字线下拉驱动器的存储器件。 行解码器包括解码电路和一组字线驱动器。 解码电路被配置为接收地址信息并产生一组字线控制信号。 字线驱动器耦合到解码电路并且响应于字线控制信号。 每个字线驱动器被配置为提供上拉驱动能力，并且还可以被配置为提供下拉驱动能力。 每个字线耦合到至少一个字线驱动器。 字线下拉驱动器耦合到字线，每个字线下拉驱动器被配置为提供下拉驱动能力。 可以沿着每个字线的长度分布（即，均匀地）一个或多个字线下拉驱动器。 字线还可以使用包括一组主字线（即，在金属层上制造）和一组分段字线（即，在多晶硅层上制造的）的分层字线结构来实现，耦合到每个主线 字线。
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