公开(公告)号：US20050045947A1

公开(公告)日：2005-03-03

申请号：US10604907

申请日：2003-08-26

申请人： Huajie Chen ,  Bruce Doris ,  Philip Oldiges ,  Xinlin Wang ,  Huilong Zhu

发明人： Huajie Chen ,  Bruce Doris ,  Philip Oldiges ,  Xinlin Wang ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/76 ,  H01L29/745 ,  H01L31/062

CPC分类号： H01L29/78696 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78684

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin (smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer. Source/drain regions are located in recesses at either end of the thin channel and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain extensions and corresponding source/drain regions are self aligned to the FET gate and thin channel.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 器件具有薄沟道，例如超薄（小于或等于10纳米（10nm））绝缘体上硅（SOI）层。 源极/漏极区位于薄沟道的任一端的凹槽中，并且比薄沟道基本上更厚（例如，30nm）。 源/漏扩展和相应的源极/漏极区域与FET栅极和薄沟道自对准。

公开(公告)号：US20050189589A1

公开(公告)日：2005-09-01

申请号：US10708378

申请日：2004-02-27

申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L27/01 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20080090366A1

公开(公告)日：2008-04-17

申请号：US11870436

申请日：2007-10-11

申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20070181930A1

公开(公告)日：2007-08-09

申请号：US10711182

申请日：2004-08-31

申请人： Huilong Zhu ,  Bruce Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip Oldiges

发明人： Huilong Zhu ,  Bruce Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip Oldiges

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

摘要翻译： 提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸， 所述主体具有与所述第一侧相对的第一侧和第二侧。 门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。 门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。 在一个实施例中，第一栅极和第二栅极彼此电隔离。 在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

公开(公告)号：US20070170507A1

公开(公告)日：2007-07-26

申请号：US11693377

申请日：2007-03-29

申请人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikei Ieong ,  Min Yang ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikei Ieong ,  Min Yang ,  Huajie Chen

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1207 ,  Y10S438/938

摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

摘要翻译： 本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

公开(公告)号：US20060172495A1

公开(公告)日：2006-08-03

申请号：US10905978

申请日：2005-01-28

申请人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikel Ioeng ,  Min Yang ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikel Ioeng ,  Min Yang ,  Huajie Chen

IPC分类号： H01L21/8234

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1207 ,  Y10S438/938

摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

摘要翻译： 本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

公开(公告)号：US20060237790A1

公开(公告)日：2006-10-26

申请号：US11473835

申请日：2006-06-23

申请人： Huilong Zhu ,  Bruce Doris ,  Meikei Ieong ,  Philip Oldiges ,  Min Yang

发明人： Huilong Zhu ,  Bruce Doris ,  Meikei Ieong ,  Philip Oldiges ,  Min Yang

IPC分类号： H01L27/12

CPC分类号： H01L21/76254 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785 ,  Y10T428/249921 ,  Y10T428/249922

摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

摘要翻译： 本发明提供一种形成具有多个结晶取向的基本上平面的SOI衬底的方法，包括以下步骤：在单个取向层的顶部提供多个取向表面，所述多个取向表面包括与第一器件区域接触并具有与 单取向层和通过绝缘材料与第一器件区域和单取向层分离的第二器件区域，其中第一器件区域和第二器件区域具有不同的晶体取向; 在单取向层产生损坏的界面; 将晶片接合到所述多个取向表面; 在损坏的界面处分离单个取向层; 其中所述单取向层的损伤表面保留; 以及平坦化损坏的表面，直到第一器件区域的表面基本上与第二器件区域的表面共面。

公开(公告)号：US20060003554A1

公开(公告)日：2006-01-05

申请号：US10710277

申请日：2004-06-30

申请人： Huilong Zhu ,  Bruce Doris ,  Meikei Ieong ,  Philip Oldiges ,  Min Yang

发明人： Huilong Zhu ,  Bruce Doris ,  Meikei Ieong ,  Philip Oldiges ,  Min Yang

IPC分类号： C30B1/00 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L21/76254 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785 ,  Y10T428/249921 ,  Y10T428/249922

摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

摘要翻译： 本发明提供一种形成具有多个结晶取向的基本上平面的SOI衬底的方法，包括以下步骤：在单个取向层的顶部提供多个取向表面，所述多个取向表面包括与第一器件区域接触并具有与 单取向层和通过绝缘材料与第一器件区域和单取向层分离的第二器件区域，其中第一器件区域和第二器件区域具有不同的晶体取向; 在单取向层产生损坏的界面; 将晶片接合到所述多个取向表面; 在损坏的界面处分离单个取向层; 其中所述单取向层的损伤表面保留; 以及平坦化损坏的表面，直到第一器件区域的表面基本上与第二器件区域的表面共面。

公开(公告)号：US20060220152A1

公开(公告)日：2006-10-05

申请号：US11095373

申请日：2005-03-31

申请人： Elbert Huang ,  Philip Oldiges ,  Ghavam Shahidi ,  Christy Tyberg ,  Xinlin Wang ,  Robert Wisnieff

发明人： Elbert Huang ,  Philip Oldiges ,  Ghavam Shahidi ,  Christy Tyberg ,  Xinlin Wang ,  Robert Wisnieff

IPC分类号： H01L29/78 ,  H01L21/469

CPC分类号： H01L29/4991 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Disclosed is a MOSFET structure and method of fabricating the structure that incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. In one embodiment, the multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. In another embodiment, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. Either embodiment may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

摘要翻译： 公开了一种MOSFET结构和制造该结构的方法，该结构包括多层侧壁间隔物以抑制栅极导体和源/漏扩展之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET的性能。 在一个实施例中，多层侧壁间隔物形成有具有等于1的介电常数的间隙层和可渗透的低K（例如，小于3.5）的电介质层。 在另一个实施例中，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二介电层。 任一实施例也可以具有第三氮化物或氧化物隔离层。 该第三间隔层提供增加的结构完整性。

公开(公告)号：US07776725B2

公开(公告)日：2010-08-17

申请号：US11162478

申请日：2005-09-12

申请人： Huilong Zhu ,  Philip Oldiges ,  Cheruvu S. Murthy

发明人： Huilong Zhu ,  Philip Oldiges ,  Cheruvu S. Murthy

IPC分类号： H01L21/04

CPC分类号： H01L21/26586 ,  H01L21/2652 ,  H01L21/28247 ,  H01L29/1045 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621

摘要： An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length. The method includes doping a short channel device and a long channel device with a first dopant, and doping the short channel device and the long channel device with a second dopant at a same implantation energy, dose, and angle for both the short channel device and the long channel device. The second dopant neutralizes the first dopant in portion to a gate length of the short channel device and the second channel device.

摘要翻译： 一种用于根据栅极长度控制半导体器件的有源区域中的净掺杂的装置和方法。 该方法包括用第一掺杂剂掺杂短沟道器件和长沟道器件，并以相同的注入能量，剂量和角度对短沟道器件和长沟道器件掺杂第二掺杂剂，以便短沟道器件和 长通道设备。 第二掺杂剂部分地将第一掺杂剂中和到短沟道器件和第二通道器件的栅极长度。