-
1.发明授权Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions 有权制造应变半导体CMOS晶体管的结构和方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域公开(公告)号：US06891192B2
公开(公告)日：2005-05-10
申请号：US10604607
申请日：2003-08-04
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L31/036
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译： 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。
-
2.发明授权Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions 有权制造应变半导体晶体管的方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域公开(公告)号：US07396714B2
公开(公告)日：2008-07-08
申请号：US11820303
申请日：2007-06-18
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译： 提供了用于制造PFET和NFET的工艺。 与栅堆叠相邻的第一半导体区域中的区域是凹进的。 在凹槽中生长晶格不匹配的半导体层以向与其相邻的PFET的沟道区施加应变。 可以在晶格失配的半导体层上生长第一半导体材料层，以及由硅层形成的硅化物以提供低电阻源极和漏极区域。
-
3.发明授权Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions 失效制造应变半导体晶体管的方法，所述半导体晶体管具有位于源极和漏极区域之下的晶格失配的半导体区域公开(公告)号：US07291528B2
公开(公告)日：2007-11-06
申请号：US11081271
申请日：2005-03-16
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译： 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。
-
公开(公告)号：US07170126B2
公开(公告)日：2007-01-30
申请号：US10605227
申请日：2003-09-16
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L27/10888
摘要： A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces resistance on the bitline contact.
摘要翻译： SiGe晶片中的沟槽电容器垂直晶体管DRAM单元通过在沟槽壁上形成外延应变硅层来补偿衬垫氮化物的突出，从而提高晶体管的迁移率，从多沟槽填充中去除空隙并降低位线接触的电阻。
-
公开(公告)号：US08119472B2
公开(公告)日：2012-02-21
申请号：US11757883
申请日：2007-06-04
IPC分类号： H01L21/8238
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。
-
公开(公告)号：US07198995B2
公开(公告)日：2007-04-03
申请号：US10733378
申请日：2003-12-12
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the nFET fin.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。 在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。 在具有硬掩模的finFET的侧壁上生长Si外延层，现在是处于张力下的封盖层，防止nFET鳍的横向屈曲。
-
公开(公告)号：US07247534B2
公开(公告)日：2007-07-24
申请号：US10715400
申请日：2003-11-19
IPC分类号： H01L21/237 , H01L21/8238 , H01L21/336 , H01L21/331 , H01L21/20 , H01L21/76
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。
-
公开(公告)号：US07223994B2
公开(公告)日：2007-05-29
申请号：US10859736
申请日：2004-06-03
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L21/0336
CPC分类号： H01L29/78 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.
摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅 层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。
-
公开(公告)号：US08232153B2
公开(公告)日：2012-07-31
申请号：US11757874
申请日：2007-06-04
IPC分类号： H01L21/337 , H01L21/8238 , H01L29/00
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。
-
公开(公告)号：US07560328B2
公开(公告)日：2009-07-14
申请号：US11694373
申请日：2007-03-30
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrates a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.
摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含硅部分，衬底的含Si部分顶部的压缩层，以及半导体硅层 在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。
-
-
-
-
-
-
-
-
-
搜索结果
32 条记录 (耗时 0.029 秒)