公开(公告)号：US12068202B2

公开(公告)日：2024-08-20

申请号：US17244410

申请日：2021-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sunhom Steve Paak ,  Xiaolong Ma ,  Yanxiang Liu ,  Daxiang Wang ,  Zanfeng Chen ,  Yu Xia ,  Huabin Chen ,  Yongjie Zhou

IPC: H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823481 ,  H01L21/0259 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. A part that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

公开(公告)号：US11043575B2

公开(公告)日：2021-06-22

申请号：US16417544

申请日：2019-05-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiaolong Ma ,  Riqing Zhang ,  Stephane Badel

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/76

Abstract: The invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove,; and forming a source and a drain in a preset source drain area along the gate length direction.

公开(公告)号：US11664440B2

公开(公告)日：2023-05-30

申请号：US17352161

申请日：2021-06-18

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiaolong Ma ,  Riqing Zhang ,  Stephane Badel

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/76

CPC classification number: H01L29/66545 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66787 ,  H01L29/7613 ,  H01L29/785

Abstract: An embodiment of the invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove; and forming a source and a drain in a preset source drain area along the gate length direction.

公开(公告)号：US20210249311A1

公开(公告)日：2021-08-12

申请号：US17244410

申请日：2021-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sunhom Steve Paak ,  Xiaolong Ma ,  Yanxiang Liu ,  Daxiang Wang ,  Zanfeng Chen ,  Yu Xia ,  Huabin Chen ,  Yongjie Zhou

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. Apart that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.